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pci ascii header

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This commit is contained in:
Jack Halford 2019-08-20 20:39:36 +02:00
parent 28175d9336
commit 9fd40142fa
2 changed files with 25 additions and 11 deletions
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17
src/pci.zig
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@ -24,7 +24,7 @@ pub const PciDevice = struct {
pub fn init(bus: u8, slot: u5, function: u3) ?PciDevice { pub fn init(bus: u8, slot: u5, function: u3) ?PciDevice {
var dev = PciDevice{ .bus = bus, .slot = slot, .function = function }; var dev = PciDevice{ .bus = bus, .slot = slot, .function = function };
dev.vendor = dev.config_read(u16, 0); dev.vendor = dev.vendor();
if (dev.vendor == 0xffff) return null; if (dev.vendor == 0xffff) return null;
return dev; return dev;
} }
@ -65,7 +65,20 @@ pub const PciDevice = struct {
return null; return null;
} }
// all pci device must implement these // 0 1 2 3
// 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// | vendor ID | device ID |
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// | command | status |
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// | revision ID | prog IF | subclass | class |
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
// |cache line size| latency timer | header type | bist |
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
pub fn vendor(self: PciDevice) u16 {
return self.config_read(u16, 0x0);
}
pub fn device(self: PciDevice) u16 { pub fn device(self: PciDevice) u16 {
return self.config_read(u16, 0x2); return self.config_read(u16, 0x2);
} }

19
src/virtio.zig
View file

@ -1,6 +1,4 @@
usingnamespace @import("vga.zig"); usingnamespace @import("kernel");
usingnamespace @import("pci.zig");
const assert = @import("std").debug.assert;
pub fn init(pci: PciDevice) void { pub fn init(pci: PciDevice) void {
println("-- virtio-block init --"); println("-- virtio-block init --");
@ -11,11 +9,14 @@ pub fn init(pci: PciDevice) void {
const intr_pin = pci.config_read(u8, 0x3d); const intr_pin = pci.config_read(u8, 0x3d);
const min_grant = pci.config_read(u8, 0x3e); const min_grant = pci.config_read(u8, 0x3e);
const max_lat = pci.config_read(u8, 0x3f); const max_lat = pci.config_read(u8, 0x3f);
println("{x} {} {} {}", intr_line, intr_pin, min_grant, max_lat); println("{x} {} {} {}", intr_line, intr_pin, min_grant, max_lat);
println("bar0=0x{x}", pci.config_read(u32, 0x10)); println("dev features =0x{x}", pci.config_read(u32, 0x10));
println("bar1=0x{x}", pci.config_read(u32, 0x14)); println("guest features=0x{x}", pci.config_read(u32, 0x14));
println("bar2=0x{x}", pci.config_read(u32, 0x18)); println("queue addr =0x{x}", pci.config_read(u32, 0x18));
println("bar3=0x{x}", pci.config_read(u32, 0x1c)); println("queue size =0x{x}", pci.config_read(u16, 0x1c));
println("bar4=0x{x}", pci.config_read(u32, 0x20)); println("queue select =0x{x}", pci.config_read(u16, 0x1e));
println("bar5=0x{x}", pci.config_read(u32, 0x24)); println("queue notify =0x{x}", pci.config_read(u16, 0x20));
println("device status =0x{x}", pci.config_read(u8, 0x22));
println("isr status =0x{x}", pci.config_read(u8, 0x23));
} }