compiles now, new import architecture
This commit is contained in:
parent
888b51282d
commit
bdc3b2939b
18 changed files with 113 additions and 300 deletions
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@ -7,7 +7,6 @@ pub fn build(b: *Builder) void {
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kernel.addPackagePath("x86", "src/arch/x86/index.zig");
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kernel.setOutputDir("build");
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// kernel.addAssemblyFile("src/arch/x86/_start.s");
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kernel.addAssemblyFile("src/arch/x86/gdt.s");
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kernel.addAssemblyFile("src/arch/x86/isr.s");
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kernel.addAssemblyFile("src/arch/x86/paging.s");
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2
qemu.sh
2
qemu.sh
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@ -12,8 +12,8 @@ start() {
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-m 1337M \
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-curses \
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-append "Hello" \
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-drive file=disk.img,if=virtio\
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-kernel ${KERNEL}
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# -drive file=disk.img,if=virtio\
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# -no-reboot \
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# -device virtio-net,netdev=network0 -netdev tap,id=network0,ifname=tap0,script=no,downscript=no \
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# build/kernel.iso
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@ -1,16 +0,0 @@
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.global __start
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.type __start, @function
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// Entry point. It puts the machine into a consistent state,
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// starts the kernel and then waits forever.
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__start:
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mov $0x80000, %esp // Setup the stack.
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push %ebx // Pass multiboot info structure.
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push %eax // Pass multiboot magic code.
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call kmain // Call the kernel.
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// Halt the CPU.
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cli
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hlt
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@ -1,18 +1,19 @@
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// https://wiki.osdev.org/IDT
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usingnamespace @import("kernel");
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usingnamespace @import("x86");
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// usingnamespace @import("kernel");
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// usingnamespace @import("x86");
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usingnamespace @import("index.zig");
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// Types of gates.
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pub const INTERRUPT_GATE = 0x8E;
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pub const SYSCALL_GATE = 0xEE;
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// Interrupt Descriptor Table.
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var idt: [256]IDTEntry = undefined;
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var idt_table: [256]IDTEntry = undefined;
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// IDT descriptor register pointing at the IDT.
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const idtr = IDTRegister{
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.limit = u16(@sizeOf(@typeOf(idt))),
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.base = &idt,
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.limit = u16(@sizeOf(@typeOf(idt_table))),
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.base = &idt_table,
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};
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// Structure representing an entry in the IDT.
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@ -40,11 +41,11 @@ const IDTRegister = packed struct {
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pub fn setGate(n: u8, flags: u8, offset: extern fn () void) void {
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const intOffset = @ptrToInt(offset);
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idt[n].offset_low = @truncate(u16, intOffset);
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idt[n].offset_high = @truncate(u16, intOffset >> 16);
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idt[n].flags = flags;
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idt[n].zero = 0;
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idt[n].selector = gdt.KERNEL_CODE;
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idt_table[n].offset_low = @truncate(u16, intOffset);
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idt_table[n].offset_high = @truncate(u16, intOffset >> 16);
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idt_table[n].flags = flags;
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idt_table[n].zero = 0;
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idt_table[n].selector = gdt.KERNEL_CODE;
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}
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// Initialize the Interrupt Descriptor Table.
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@ -1,9 +1,15 @@
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usingnamespace @import("lib/io.zig");
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usingnamespace @import("lib/instructions.zig");
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usingnamespace @import("main.zig");
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pub usingnamespace @import("../../vga.zig");
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pub const multiboot = @import("../../multiboot.zig");
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const memory = @import("memory.zig");
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const paging = @import("paging.zig");
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const idt = @import("idt.zig");
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const gdt = @import("gdt.zig");
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const interrupt = @import("interrupt.zig");
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pub usingnamespace @import("lib/io.zig");
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pub usingnamespace @import("lib/instructions.zig");
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pub usingnamespace @import("main.zig");
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pub const memory = @import("memory.zig");
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pub const paging = @import("paging.zig");
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pub const idt = @import("idt.zig");
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pub const isr = @import("isr.zig");
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pub const gdt = @import("gdt.zig");
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pub const interrupt = @import("interrupt.zig");
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pub const assert = @import("std").debug.assert;
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@ -1,6 +1,6 @@
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usingnamespace @import("kernel");
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const x86 = @import("x86");
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const isr = @import("isr.zig");
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usingnamespace @import("index.zig");
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// const x86 = @import("index.zig");
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// const isr = @import("isr.zig");
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// PIC ports.
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const PIC1_CMD = 0x20;
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@ -32,16 +32,17 @@ var handlers = [_]fn () void{unhandled} ** 48;
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fn unhandled() noreturn {
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const n = isr.context.interrupt_n;
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print("unhandled interrupt number {d}", n);
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if (n < IRQ_0) {
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println("unhandled exception number {d}", n);
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println(" (exception)");
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} else {
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println("unhandled IRQ number {d} (intr {d})", n - IRQ_0, n);
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println(" (IRQ number {d})", n - IRQ_0);
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}
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x86.hang();
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hang();
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}
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inline fn picwait() void {
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x86.outb(WAIT_PORT, 0);
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outb(WAIT_PORT, 0);
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}
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////
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@ -81,8 +82,8 @@ export fn interruptDispatch() void {
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// If no user thread is ready to run, halt here and wait for interrupts.
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// if (scheduler.current() == null) {
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// x86.sti();
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// x86.hlt();
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// sti();
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// hlt();
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// }
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}
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@ -92,8 +93,8 @@ inline fn spuriousIRQ(irq: u8) bool {
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// TODO: handle spurious IRQ15.
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// Read the value of the In-Service Register.
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x86.outb(PIC1_CMD, ISR_READ);
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const in_service = x86.inb(PIC1_CMD);
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outb(PIC1_CMD, ISR_READ);
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const in_service = inb(PIC1_CMD);
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// Verify whether IRQ7 is set in the ISR.
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return (in_service & (1 << 7)) == 0;
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@ -103,11 +104,11 @@ inline fn startOfInterrupt(irq: u8) void {
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// mask the irq and then ACK
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if (irq >= 8) {
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maskIRQ(irq, true);
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x86.outb(PIC1_CMD, ACK);
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x86.outb(PIC2_CMD, ACK);
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outb(PIC1_CMD, ACK);
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outb(PIC2_CMD, ACK);
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} else {
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maskIRQ(irq, true);
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x86.outb(PIC1_CMD, ACK);
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outb(PIC1_CMD, ACK);
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}
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}
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@ -115,10 +116,10 @@ inline fn endOfInterrupt(irq: u8) void {
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// unmask the irq and then ACK
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if (irq >= 8) {
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maskIRQ(irq, false);
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x86.outb(PIC2_CMD, ACK);
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outb(PIC2_CMD, ACK);
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} else {
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maskIRQ(irq, false);
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x86.outb(PIC1_CMD, ACK);
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outb(PIC1_CMD, ACK);
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}
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}
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@ -133,33 +134,33 @@ pub fn registerIRQ(irq: u8, handler: fn () void) void {
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fn remapPIC() void {
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// ICW1: start initialization sequence.
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x86.outb(PIC1_CMD, ICW1_INIT | ICW1_ICW4);
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outb(PIC1_CMD, ICW1_INIT | ICW1_ICW4);
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picwait();
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x86.outb(PIC2_CMD, ICW1_INIT | ICW1_ICW4);
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outb(PIC2_CMD, ICW1_INIT | ICW1_ICW4);
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picwait();
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// ICW2: Interrupt Vector offsets of IRQs.
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x86.outb(PIC1_DATA, IRQ_0); // IRQ 0..7 -> Interrupt 32..39
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outb(PIC1_DATA, IRQ_0); // IRQ 0..7 -> Interrupt 32..39
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picwait();
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x86.outb(PIC2_DATA, IRQ_0 + 8); // IRQ 8..15 -> Interrupt 40..47
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outb(PIC2_DATA, IRQ_0 + 8); // IRQ 8..15 -> Interrupt 40..47
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picwait();
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// ICW3: IRQ line 2 to connect master to slave PIC.
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x86.outb(PIC1_DATA, 1 << 2);
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outb(PIC1_DATA, 1 << 2);
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picwait();
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x86.outb(PIC2_DATA, 2);
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outb(PIC2_DATA, 2);
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picwait();
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// ICW4: 80x86 mode.
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x86.outb(PIC1_DATA, ICW4_8086);
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outb(PIC1_DATA, ICW4_8086);
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picwait();
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x86.outb(PIC2_DATA, ICW4_8086);
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outb(PIC2_DATA, ICW4_8086);
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picwait();
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// Mask all IRQs.
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x86.outb(PIC1_DATA, 0xFF);
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outb(PIC1_DATA, 0xFF);
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picwait();
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x86.outb(PIC2_DATA, 0xFF);
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outb(PIC2_DATA, 0xFF);
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picwait();
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}
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@ -167,16 +168,16 @@ pub fn maskIRQ(irq: u8, mask: bool) void {
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if (irq > 15) return;
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// Figure out if master or slave PIC owns the IRQ.
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const port = if (irq < 8) u16(PIC1_DATA) else u16(PIC2_DATA);
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const old = x86.inb(port); // Retrieve the current mask.
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const old = inb(port); // Retrieve the current mask.
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// Mask or unmask the interrupt.
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const shift = @intCast(u3, irq % 8);
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if (mask) {
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x86.outb(port, old | (u8(1) << shift));
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outb(port, old | (u8(1) << shift));
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} else {
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x86.outb(port, old & ~(u8(1) << shift));
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outb(port, old & ~(u8(1) << shift));
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}
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const new = x86.inb(port); // Retrieve the current mask.
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const new = inb(port); // Retrieve the current mask.
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}
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////
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@ -1,4 +1,4 @@
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usingnamespace @import("x86");
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usingnamespace @import("index.zig");
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// Interrupt Service Routines defined externally in assembly.
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extern fn isr0() void;
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@ -1,13 +1,14 @@
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usingnamespace @import("kernel");
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usingnamespace @import("x86");
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// usingnamespace @import("kernel");
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usingnamespace @import("index.zig");
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// const multiboot = @import("../../multiboot.zig");
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/// x86 specific intialization
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pub fn x86_main(info: *const MultibootInfo) void {
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pub fn x86_main(info: *const multiboot.MultibootInfo) void {
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gdt.initialize();
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idt.initialize();
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memory.initialize(info);
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paging.initialize();
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// enable interrupts
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x86.sti();
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sti();
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}
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@ -1,4 +1,4 @@
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usingnamespace @import("kernel");
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usingnamespace @import("index.zig");
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var stack: [*]usize = undefined; // Stack of free physical page.
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var stack_index: usize = 0; // Index into the stack.
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@ -51,10 +51,10 @@ pub fn free(address: usize) void {
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// Arguments:
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// info: Information structure from bootloader.
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//
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pub fn initialize(info: *const MultibootInfo) void {
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pub fn initialize(info: *const multiboot.MultibootInfo) void {
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// Ensure the bootloader has given us the memory map.
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assert((info.flags & MULTIBOOT_INFO_MEMORY) != 0);
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assert((info.flags & MULTIBOOT_INFO_MEM_MAP) != 0);
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assert((info.flags & multiboot.MULTIBOOT_INFO_MEMORY) != 0);
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assert((info.flags & multiboot.MULTIBOOT_INFO_MEM_MAP) != 0);
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// Place the stack of free pages after the last Multiboot module.
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stack = @intToPtr([*]usize, 0x200000);
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@ -65,7 +65,7 @@ pub fn initialize(info: *const MultibootInfo) void {
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var map: usize = info.mmap_addr;
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while (map < info.mmap_addr + info.mmap_length) {
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var entry = @intToPtr(*MultibootMMapEntry, map);
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var entry = @intToPtr(*multiboot.MultibootMMapEntry, map);
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// Calculate the start and end of this memory area.
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var start = @truncate(usize, entry.addr);
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@ -74,7 +74,7 @@ pub fn initialize(info: *const MultibootInfo) void {
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start = if (start >= stack_end) start else stack_end;
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// Flag all the pages in this memory area as free.
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if (entry.type == MULTIBOOT_MEMORY_AVAILABLE) while (start < end) : (start += PAGE_SIZE)
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if (entry.type == multiboot.MULTIBOOT_MEMORY_AVAILABLE) while (start < end) : (start += PAGE_SIZE)
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free(start);
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// Go to the next entry in the memory map.
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@ -1,5 +1,5 @@
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usingnamespace @import("kernel");
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usingnamespace @import("x86");
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usingnamespace @import("index.zig");
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// usingnamespace @import("x86");
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extern fn setupPaging(phys_pd: usize) void;
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@ -1,4 +1,4 @@
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usingnamespace @import("kernel");
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usingnamespace @import("index.zig");
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var command: [10]u8 = undefined;
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var command_len: usize = 0;
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@ -30,6 +30,6 @@ pub fn keypress(char: u8) void {
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}
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pub fn initialize() void {
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@import("x86").interrupt.registerIRQ(1, ps2.keyboard_handler);
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x86.interrupt.registerIRQ(1, ps2.keyboard_handler);
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print("> ");
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}
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@ -1,8 +1,9 @@
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pub const assert = @import("std").debug.assert;
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pub const std = @import("std");
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pub usingnamespace @import("vga.zig");
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pub const main = @import("main.zig");
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pub const multiboot = @import("multiboot.zig");
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pub const console = @import("console.zig");
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pub const pci = @import("pci.zig");
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pub const pci = @import("pci/pci.zig");
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pub const ps2 = @import("ps2.zig");
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pub const assert = @import("std").debug.assert;
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pub const x86 = @import("arch/x86/index.zig");
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32
src/main.zig
32
src/main.zig
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@ -1,29 +1,43 @@
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usingnamespace @import("kernel");
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// const x86 = @import("x86");
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const x86 = @import("x86");
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// Place the header at the very beginning of the binary.
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export const multiboot_header align(4) linksection(".multiboot") = multiboot: {
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const MAGIC = u32(0x1BADB002); // multiboot magic
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const ALIGN = u32(1 << 0); // Align loaded modules at 4k
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const MEMINFO = u32(1 << 1); // Receive a memory map from the bootloader.
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const ADDR = u32(1 << 16); // Load specific addr
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const FLAGS = ALIGN | MEMINFO; // Combine the flags.
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break :multiboot multiboot.MultibootHeader{
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.magic = MAGIC,
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.flags = FLAGS,
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.checksum = ~(MAGIC +% FLAGS) +% 1,
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};
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};
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export var stack_bytes: [16 * 1024]u8 align(16) linksection(".bss") = undefined;
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const stack_bytes_slice = stack_bytes[0..];
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// linker.ld entrypoint
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export nakedcc fn _start() noreturn {
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// ebx -> multiboot info
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const info: u32 = asm volatile (""
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: [result] "={ebx}" (-> u32)
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);
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export nakedcc fn __start() noreturn {
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// eax -> multiboot magic
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const magic: u32 = asm volatile (""
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: [result] "={eax}" (-> u32)
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);
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// ebx -> multiboot info
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const info: u32 = asm volatile (""
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: [result] "={ebx}" (-> u32)
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);
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@newStackCall(stack_bytes_slice, kmain, magic, @intToPtr(*const multiboot.MultibootInfo, info));
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while (true) {}
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// @newStackCall(stack_bytes_slice, kmain);
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}
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// arch independant initialization
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fn kmain(magic: u32, info: *const multiboot.MultibootInfo) noreturn {
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assert(magic == multiboot.MULTIBOOT_BOOTLOADER_MAGIC);
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clear();
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println("--- {x} ---", magic);
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// assert(magic == multiboot.MULTIBOOT_BOOTLOADER_MAGIC);
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println("--- x86 initialization ---");
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x86.x86_main(info);
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println("--- core initialization ---");
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@ -124,7 +124,7 @@ pub const MultibootModule = packed struct {
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};
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// Multiboot structure to be read by the bootloader.
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const MultibootHeader = packed struct {
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pub const MultibootHeader = packed struct {
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magic: u32, // Must be equal to header magic number.
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flags: u32, // Feature flags.
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checksum: u32, // Above fields plus this one must equal 0 mod 2^32.
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@ -136,18 +136,3 @@ const MultibootHeader = packed struct {
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entry_addr: u32 = 0,
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};
|
||||
// NOTE: this structure is incomplete.
|
||||
|
||||
// Place the header at the very beginning of the binary.
|
||||
export const multiboot_header align(4) linksection(".multiboot") = multiboot: {
|
||||
const MAGIC = u32(0x1BADB002); // multiboot magic
|
||||
const ALIGN = u32(1 << 0); // Align loaded modules at 4k
|
||||
const MEMINFO = u32(1 << 1); // Receive a memory map from the bootloader.
|
||||
const ADDR = u32(1 << 16); // Load specific addr
|
||||
const FLAGS = ALIGN | MEMINFO; // Combine the flags.
|
||||
|
||||
break :multiboot MultibootHeader{
|
||||
.magic = MAGIC,
|
||||
.flags = FLAGS,
|
||||
.checksum = ~(MAGIC +% FLAGS) +% 1,
|
||||
};
|
||||
};
|
||||
|
|
|
|||
157
src/pci.zig
157
src/pci.zig
|
|
@ -1,157 +0,0 @@
|
|||
usingnamespace @import("kernel");
|
||||
const arch = @import("x86");
|
||||
const std = @import("std");
|
||||
const virtio = @import("virtio.zig");
|
||||
|
||||
const PCI_CONFIG_ADDRESS = 0xCF8;
|
||||
const PCI_CONFIG_DATA = 0xCFC;
|
||||
|
||||
// https://wiki.osdev.org/Pci
|
||||
pub const PciAddress = packed struct {
|
||||
offset: u8,
|
||||
function: u3,
|
||||
slot: u5,
|
||||
bus: u8,
|
||||
reserved: u7,
|
||||
enable: u1,
|
||||
};
|
||||
|
||||
pub const PciDevice = struct {
|
||||
bus: u8,
|
||||
slot: u5,
|
||||
function: u3,
|
||||
vendor: u16 = undefined,
|
||||
|
||||
pub fn init(bus: u8, slot: u5, function: u3) ?PciDevice {
|
||||
var dev = PciDevice{ .bus = bus, .slot = slot, .function = function };
|
||||
dev.vendor = dev.vendor();
|
||||
if (dev.vendor == 0xffff) return null;
|
||||
return dev;
|
||||
}
|
||||
|
||||
pub fn address(self: PciDevice, offset: u8) u32 {
|
||||
var addr = PciAddress{
|
||||
.enable = 1,
|
||||
.reserved = 0,
|
||||
.bus = self.bus,
|
||||
.slot = self.slot,
|
||||
.function = self.function,
|
||||
.offset = offset,
|
||||
};
|
||||
return @bitCast(u32, addr);
|
||||
}
|
||||
|
||||
pub fn format(self: PciDevice) void {
|
||||
print("{}:{}.{}", self.bus, self.slot, self.function);
|
||||
print(" {x},{x:2}", self.class(), self.subclass());
|
||||
print(" 0x{x},0x{x}", self.vendor, self.device());
|
||||
if (self.driver()) |d|
|
||||
print(" {}", d.name);
|
||||
println("");
|
||||
}
|
||||
|
||||
pub fn driver(self: PciDevice) ?Driver {
|
||||
var i: usize = 0;
|
||||
while (i < Drivers.len) : (i += 1) {
|
||||
var drv = Drivers[i];
|
||||
if (self.class() != drv.class or self.subclass() != drv.subclass)
|
||||
continue;
|
||||
if (drv.vendor) |v| if (self.vendor != v)
|
||||
continue;
|
||||
if (drv.subsystem) |ss| if (self.subsystem() != ss)
|
||||
continue;
|
||||
return drv;
|
||||
}
|
||||
return null;
|
||||
}
|
||||
|
||||
// 0 1 2 3
|
||||
// 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
|
||||
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
// | vendor ID | device ID |
|
||||
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
// | command | status |
|
||||
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
// | revision ID | prog IF | subclass | class |
|
||||
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
// |cache line size| latency timer | header type | bist |
|
||||
// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
pub fn vendor(self: PciDevice) u16 {
|
||||
return self.config_read(u16, 0x0);
|
||||
}
|
||||
pub fn device(self: PciDevice) u16 {
|
||||
return self.config_read(u16, 0x2);
|
||||
}
|
||||
pub fn subclass(self: PciDevice) u8 {
|
||||
return self.config_read(u8, 0xa);
|
||||
}
|
||||
pub fn class(self: PciDevice) u8 {
|
||||
return self.config_read(u8, 0xb);
|
||||
}
|
||||
pub fn header_type(self: PciDevice) u8 {
|
||||
return self.config_read(u8, 0xe);
|
||||
}
|
||||
|
||||
// only for header_type == 0
|
||||
pub fn subsystem(self: PciDevice) u16 {
|
||||
return self.config_read(u8, 0x2e);
|
||||
}
|
||||
|
||||
pub inline fn config_read(self: PciDevice, comptime size: type, comptime offset: u8) size {
|
||||
// ask for access before reading config
|
||||
arch.outl(PCI_CONFIG_ADDRESS, self.address(offset));
|
||||
switch (size) {
|
||||
// read the correct size
|
||||
u8 => return arch.inb(PCI_CONFIG_DATA),
|
||||
u16 => return arch.inw(PCI_CONFIG_DATA),
|
||||
u32 => return arch.inl(PCI_CONFIG_DATA),
|
||||
else => @compileError("pci config space only supports reading u8, u16, u32."),
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
const Driver = struct {
|
||||
name: [*]u8,
|
||||
class: u8,
|
||||
subclass: u8,
|
||||
vendor: ?u16 = null,
|
||||
subsystem: ?u16 = null,
|
||||
init: fn (PciDevice) void,
|
||||
};
|
||||
|
||||
const name = "virtio-blk";
|
||||
pub var Drivers: [1]Driver = [_]Driver{Driver{ .name = &name, .class = 0x1, .subclass = 0x0, .vendor = 0x1af4, .subsystem = 0x2, .init = virtio.init }};
|
||||
|
||||
// TODO: factor 2 functions when anonymous fn is released
|
||||
pub fn scan() void {
|
||||
var slot: u5 = 0;
|
||||
// 0..31
|
||||
while (slot <= std.math.maxInt(u5)) : (slot += 1) {
|
||||
if (PciDevice.init(0, slot, 0)) |dev| {
|
||||
var function: u3 = 0;
|
||||
// 0..7
|
||||
while (function <= std.math.maxInt(u3)) : (function += 1) {
|
||||
if (PciDevice.init(0, slot, function)) |vf| {
|
||||
if (vf.driver()) |d| d.init(vf);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub fn lspci() void {
|
||||
var slot: u5 = 0;
|
||||
println("b:s.f c,s v d drv");
|
||||
// 0..31
|
||||
while (slot <= std.math.maxInt(u5)) : (slot += 1) {
|
||||
if (PciDevice.init(0, slot, 0)) |dev| {
|
||||
var function: u3 = 0;
|
||||
// 0..7
|
||||
while (function <= std.math.maxInt(u3)) : (function += 1) {
|
||||
if (PciDevice.init(0, slot, function)) |vf| {
|
||||
vf.format();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
usingnamespace @import("kernel");
|
||||
const x86 = @import("x86");
|
||||
usingnamespace @import("index.zig");
|
||||
// const x86 = @import("x86");
|
||||
|
||||
const PS2_DATA = 0x60;
|
||||
const PS2_STATUS = 0x64;
|
||||
|
|
|
|||
18
src/vga.zig
18
src/vga.zig
|
|
@ -1,4 +1,4 @@
|
|||
const arch = @import("x86");
|
||||
const x86 = @import("arch/x86/index.zig");
|
||||
const std = @import("std");
|
||||
|
||||
// Screen size.
|
||||
|
|
@ -156,10 +156,10 @@ const VGA = struct {
|
|||
// Use the software cursor as the source of truth.
|
||||
//
|
||||
pub fn updateCursor(self: *const VGA) void {
|
||||
arch.outb(0x3D4, 0x0F);
|
||||
arch.outb(0x3D5, @truncate(u8, self.cursor));
|
||||
arch.outb(0x3D4, 0x0E);
|
||||
arch.outb(0x3D5, @truncate(u8, self.cursor >> 8));
|
||||
x86.outb(0x3D4, 0x0F);
|
||||
x86.outb(0x3D5, @truncate(u8, self.cursor));
|
||||
x86.outb(0x3D4, 0x0E);
|
||||
x86.outb(0x3D5, @truncate(u8, self.cursor >> 8));
|
||||
}
|
||||
|
||||
////
|
||||
|
|
@ -169,11 +169,11 @@ const VGA = struct {
|
|||
pub fn fetchCursor(self: *VGA) void {
|
||||
var cursor: usize = 0;
|
||||
|
||||
arch.outb(0x3D4, 0x0E);
|
||||
cursor |= usize(arch.inb(0x3D5)) << 8;
|
||||
x86.outb(0x3D4, 0x0E);
|
||||
cursor |= usize(x86.inb(0x3D5)) << 8;
|
||||
|
||||
arch.outb(0x3D4, 0x0F);
|
||||
cursor |= arch.inb(0x3D5);
|
||||
x86.outb(0x3D4, 0x0F);
|
||||
cursor |= x86.inb(0x3D5);
|
||||
|
||||
self.cursor = cursor;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,22 +0,0 @@
|
|||
usingnamespace @import("kernel");
|
||||
|
||||
pub fn init(pci: PciDevice) void {
|
||||
println("-- virtio-block init --");
|
||||
pci.format();
|
||||
assert(pci.header_type() == 0x0); // mass storage device
|
||||
assert(pci.subsystem() == 0x2); // virtio-block
|
||||
const intr_line = pci.config_read(u8, 0x3c);
|
||||
const intr_pin = pci.config_read(u8, 0x3d);
|
||||
const min_grant = pci.config_read(u8, 0x3e);
|
||||
const max_lat = pci.config_read(u8, 0x3f);
|
||||
|
||||
println("{x} {} {} {}", intr_line, intr_pin, min_grant, max_lat);
|
||||
println("dev features =0x{x}", pci.config_read(u32, 0x10));
|
||||
println("guest features=0x{x}", pci.config_read(u32, 0x14));
|
||||
println("queue addr =0x{x}", pci.config_read(u32, 0x18));
|
||||
println("queue size =0x{x}", pci.config_read(u16, 0x1c));
|
||||
println("queue select =0x{x}", pci.config_read(u16, 0x1e));
|
||||
println("queue notify =0x{x}", pci.config_read(u16, 0x20));
|
||||
println("device status =0x{x}", pci.config_read(u8, 0x22));
|
||||
println("isr status =0x{x}", pci.config_read(u8, 0x23));
|
||||
}
|
||||
Loading…
Reference in a new issue