435 lines
17 KiB
Zig
435 lines
17 KiB
Zig
usingnamespace @import("index.zig");
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const IDE_ATA = 0x00;
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const IDE_ATAPI = 0x01;
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const ATA_MASTER = 0x00;
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const ATA_SLAVE = 0x01;
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// Channels:
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const ATA_PRIMARY = 0x00;
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const ATA_SECONDARY = 0x01;
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// Directions:
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const ATA_READ = 0x00;
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const ATA_WRITE = 0x01;
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// Commands
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const ATA_CMD_READ_PIO = 0x20;
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const ATA_CMD_READ_PIO_EXT = 0x24;
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const ATA_CMD_READ_DMA = 0xC8;
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const ATA_CMD_READ_DMA_EXT = 0x25;
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const ATA_CMD_WRITE_PIO = 0x30;
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const ATA_CMD_WRITE_PIO_EXT = 0x34;
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const ATA_CMD_WRITE_DMA = 0xCA;
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const ATA_CMD_WRITE_DMA_EXT = 0x35;
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const ATA_CMD_CACHE_FLUSH = 0xE7;
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const ATA_CMD_CACHE_FLUSH_EXT = 0xEA;
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const ATA_CMD_PACKET = 0xA0;
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const ATA_CMD_IDENTIFY_PACKET = 0xA1;
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const ATA_CMD_IDENTIFY = 0xEC;
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// Status:
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const ATA_SR_BSY = 0x80; // Busy
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const ATA_SR_DRDY = 0x40; // Drive ready
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const ATA_SR_DF = 0x20; // Drive write fault
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const ATA_SR_DSC = 0x10; // Drive seek complete
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const ATA_SR_DRQ = 0x08; // Data request ready
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const ATA_SR_CORR = 0x04; // Corrected data
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const ATA_SR_IDX = 0x02; // Index
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const ATA_SR_ERR = 0x01; // Error
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// Registers:
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const ATA_REG_DATA = 0x00;
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const ATA_REG_ERROR = 0x01;
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const ATA_REG_FEATURES = 0x01;
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const ATA_REG_SECCOUNT0 = 0x02;
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const ATA_REG_LBA0 = 0x03;
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const ATA_REG_LBA1 = 0x04;
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const ATA_REG_LBA2 = 0x05;
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const ATA_REG_HDDEVSEL = 0x06;
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const ATA_REG_COMMAND = 0x07;
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const ATA_REG_STATUS = 0x07;
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const ATA_REG_SECCOUNT1 = 0x08;
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const ATA_REG_LBA3 = 0x09;
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const ATA_REG_LBA4 = 0x0A;
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const ATA_REG_LBA5 = 0x0B;
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const ATA_REG_CONTROL = 0x0C;
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const ATA_REG_ALTSTATUS = 0x0C;
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const ATA_REG_DEVADDRESS = 0x0D;
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// Identification space
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const ATA_IDENT_DEVICETYPE = 0;
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const ATA_IDENT_CYLINDERS = 2;
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const ATA_IDENT_HEADS = 6;
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const ATA_IDENT_SECTORS = 12;
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const ATA_IDENT_SERIAL = 20;
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const ATA_IDENT_MODEL = 54;
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const ATA_IDENT_CAPABILITIES = 98;
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const ATA_IDENT_FIELDVALID = 106;
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const ATA_IDENT_MAX_LBA = 120;
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const ATA_IDENT_COMMANDSETS = 164;
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const ATA_IDENT_MAX_LBA_EXT = 200;
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const ide_buf: [2048]u8 = [1]u8{0} ** 2048;
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const atapi_packet: [12]u8 = [1]u8{0xA8} ++ [1]u8{0} ** 11;
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var ide_irq_invoked = false;
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const IDEDevice = struct {
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reserved: u8, // 0 (Empty) or 1 (This Drive really exists).
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channel: u8, // 0 (Primary Channel) or 1 (Secondary Channel).
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drive: u8, // 0 (Master Drive) or 1 (Slave Drive).
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idetype: u16, // 0: ATA, 1:ATAPI.
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signature: u16, // Drive Signature
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capabilities: u16, // Features.
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commandsets: usize, // Command Sets Supported.
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size: usize, // Size in Sectors.
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model: [41]u8, // Model in string.
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};
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var ide_devices: [4]IDEDevice = undefined;
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const IDEChannelRegister = struct {
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base: u16, // I/O Base.
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ctrl: u16, // Control Base
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bmide: u16, // Bus Master IDE
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nIEN: u8, // nIEN (No Interrupt);
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};
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var channels: [2]IDEChannelRegister = undefined;
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pub inline fn ide_read(channel: u8, comptime reg: u8) u8 {
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if (reg > 0x07 and reg < 0x0C) ide_write(channel, ATA_REG_CONTROL, 0x80 | channels[channel].nIEN);
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defer if (reg > 0x07 and reg < 0x0C) ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
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return switch (reg) {
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0x0...0x7 => x86.inb(channels[channel].base + reg - 0x0),
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0x8...0xb => x86.inb(channels[channel].base + reg - 0x6),
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0xc...0xd => x86.inb(channels[channel].ctrl + reg - 0xa),
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0xe...0x16 => x86.inb(channels[channel].bmide + reg - 0xe),
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else => @compileError("bad IDE register."),
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};
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}
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pub inline fn ide_read_buffer(channel: u8, comptime reg: u8, buf: var, cnt: usize) void {
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if (reg > 0x07 and reg < 0x0C) ide_write(channel, ATA_REG_CONTROL, 0x80 | channels[channel].nIEN);
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defer if (reg > 0x07 and reg < 0x0C) ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
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switch (reg) {
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0x0...0x7 => x86.insl(channels[channel].base + reg - 0x0, buf, cnt),
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0x8...0xb => x86.insl(channels[channel].base + reg - 0x6, buf, cnt),
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0xc...0xd => x86.insl(channels[channel].ctrl + reg - 0xa, buf, cnt),
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0xe...0x16 => x86.insl(channels[channel].bmide + reg - 0xe, buf, cnt),
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else => @compileError("bad IDE register."),
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}
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}
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pub inline fn ide_write(channel: u8, comptime reg: u8, data: u8) void {
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if (reg > 0x07 and reg < 0x0C) ide_write(channel, ATA_REG_CONTROL, 0x80 | channels[channel].nIEN);
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defer if (reg > 0x07 and reg < 0x0C) ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
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switch (reg) {
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0x0...0x7 => x86.outb(channels[channel].base + reg - 0x0, data),
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0x8...0xb => x86.outb(channels[channel].base + reg - 0x6, data),
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0xc...0xd => x86.outb(channels[channel].ctrl + reg - 0xa, data),
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0xe...0x16 => x86.outb(channels[channel].bmide + reg - 0xe, data),
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else => @compileError("bad IDE register."),
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}
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}
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inline fn ide_polling(channel: u8, comptime advanced_check: bool) ?u8 {
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// (I) Delay 400 nanosecond for BSY to be set:
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for ([_]u8{ 0, 1, 2, 3 }) |_| _ = ide_read(channel, ATA_REG_ALTSTATUS); // wate 100ns per call
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while (ide_read(channel, ATA_REG_STATUS) & ATA_SR_BSY != 0) {} // Wait for BSY to be zero.
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if (advanced_check) {
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const state = ide_read(channel, ATA_REG_STATUS); // Read Status Register.
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if (state & ATA_SR_ERR != 0) return u8(2); // Error.
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if (state & ATA_SR_DF != 0) return 1; // Device Fault.
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if ((state & ATA_SR_DRQ) == 0) return 3; // DRQ should be set
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}
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return null; // No Error.
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}
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fn ide_ata_access(direction: u8, drive: u8, lba: u64, numsects: u8, selector: u16, edi: usize) u8 {
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var dma = false; // 0: No DMA, 1: DMA
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var cmd: u8 = 0;
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var lba_io = [1]u8{0} ** 8;
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const channel = ide_devices[drive].channel; // Read the Channel.
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const slavebit = ide_devices[drive].drive; // Read the Drive [Master/Slave]
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const bus: usize = channels[channel].base; // Bus Base, like 0x1F0 which is also data port.
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var words: usize = 256; // Almost every ATA drive has a sector-size of 512-byte.
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ide_irq_invoked = false;
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channels[channel].nIEN = 0x02;
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ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
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var lba_mode: u8 = undefined;
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var head: u8 = undefined;
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// (I) Select one from LBA28, LBA48 or CHS;
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if (lba >= 0x10000000) {
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// Sure Drive should support LBA in this case, or you are giving a wrong LBA.
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// LBA48:
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lba_io = @bitCast([8]u8, lba);
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head = 0; // Lower 4-bits of HDDEVSEL are not used here.
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lba_mode = 2;
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} else if (ide_devices[drive].capabilities & 0x200 != 0) { // Drive supports LBA?
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// LBA28:
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lba_io = @bitCast([8]u8, lba);
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assert(lba_io[3] == 0);
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head = @intCast(u8, (lba & 0xF000000) >> 24);
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lba_mode = 1;
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} else {
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// CHS:
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const sect = @intCast(u8, (lba % 63) + 1);
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const cyl = (lba + 1 - sect) / (16 * 63);
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lba_io[0] = sect;
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lba_io[1] = @intCast(u8, (cyl >> 0) & 0xFF);
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lba_io[2] = @intCast(u8, (cyl >> 8) & 0xFF);
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lba_io[3] = 0;
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lba_io[4] = 0;
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lba_io[5] = 0;
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head = @intCast(u8, (lba + 1 - sect) % (16 * 63) / (63)); // Head number is written to HDDEVSEL lower 4-bits.
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lba_mode = 0;
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}
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kernel.println("lba_mode {}", lba_mode);
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// (III) Wait if the drive is busy;
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while (ide_read(channel, ATA_REG_STATUS) & ATA_SR_BSY != 0) {} // Wait if busy.)
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// (IV) Select Drive from the controller;
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if (lba_mode == 0) ide_write(channel, ATA_REG_HDDEVSEL, 0xA0 | (slavebit << 4) | head); // Drive & CHS.
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if (lba_mode != 0) ide_write(channel, ATA_REG_HDDEVSEL, 0xE0 | (slavebit << 4) | head); // Drive & LBA
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// (V) Write Parameters;
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if (lba_mode == 2) {
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ide_write(channel, ATA_REG_SECCOUNT1, 0);
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ide_write(channel, ATA_REG_LBA3, lba_io[3]);
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ide_write(channel, ATA_REG_LBA4, lba_io[4]);
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ide_write(channel, ATA_REG_LBA5, lba_io[5]);
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}
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ide_write(channel, ATA_REG_SECCOUNT0, numsects);
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ide_write(channel, ATA_REG_LBA0, lba_io[0]);
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ide_write(channel, ATA_REG_LBA1, lba_io[1]);
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ide_write(channel, ATA_REG_LBA2, lba_io[2]);
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// (VI) Select the command and send it;
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if (lba_mode == 0 and direction == 0 and !dma) cmd = ATA_CMD_READ_PIO;
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if (lba_mode == 1 and direction == 0 and !dma) cmd = ATA_CMD_READ_PIO;
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if (lba_mode == 2 and direction == 0 and !dma) cmd = ATA_CMD_READ_PIO_EXT;
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if (lba_mode == 0 and direction == 0 and dma) cmd = ATA_CMD_READ_DMA;
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if (lba_mode == 1 and direction == 0 and dma) cmd = ATA_CMD_READ_DMA;
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if (lba_mode == 2 and direction == 0 and dma) cmd = ATA_CMD_READ_DMA_EXT;
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if (lba_mode == 0 and direction == 1 and !dma) cmd = ATA_CMD_WRITE_PIO;
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if (lba_mode == 1 and direction == 1 and !dma) cmd = ATA_CMD_WRITE_PIO;
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if (lba_mode == 2 and direction == 1 and !dma) cmd = ATA_CMD_WRITE_PIO_EXT;
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if (lba_mode == 0 and direction == 1 and dma) cmd = ATA_CMD_WRITE_DMA;
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if (lba_mode == 1 and direction == 1 and dma) cmd = ATA_CMD_WRITE_DMA;
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if (lba_mode == 2 and direction == 1 and dma) cmd = ATA_CMD_WRITE_DMA_EXT;
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ide_write(channel, ATA_REG_COMMAND, cmd); // Send the Command.
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if (dma) {
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//TODO: dma
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// if (direction == 0);
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// // DMA Read.
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// else;
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// // DMA Write.
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}
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if (!dma and direction == 0) {
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// PIO Read.
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var i: u8 = 0;
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var iedi = edi;
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while (i < numsects) : (i = i + 1) {
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iedi = edi + i * (words * 2);
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if (ide_polling(channel, true)) |err| return err; // Polling, set error and exit if there is.
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asm volatile ("pushw %%es");
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asm volatile ("mov %[a], %%es"
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:
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: [a] "{eax}" (selector)
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);
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asm volatile ("rep insw"
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:
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: [words] "{ecx}" (words),
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[bus] "{dx}" (bus),
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[iedi] "{edi}" (iedi)
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); // Receive Data.
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asm volatile ("popw %%es");
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}
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}
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if (!dma and direction == 1) {
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// PIO Write.
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var i: u8 = 0;
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var iedi = edi;
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while (i < numsects) : (i = i + 1) {
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iedi = edi + i * (words * 2);
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_ = ide_polling(channel, false); // Polling.
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asm volatile ("pushw %%ds");
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asm volatile ("mov %%ax, %%ds"
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:
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: [selector] "{eax}" (selector)
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);
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asm volatile ("rep outsw"
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:
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: [words] "{ecx}" (words),
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[bus] "{dx}" (bus),
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[iedi] "{esi}" (iedi)
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); // Send Data
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asm volatile ("popw %%ds");
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}
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if (lba_mode == 2) ide_write(channel, ATA_REG_COMMAND, ATA_CMD_CACHE_FLUSH_EXT);
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if (lba_mode != 2) ide_write(channel, ATA_REG_COMMAND, ATA_CMD_CACHE_FLUSH);
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_ = ide_polling(channel, true); // Polling.
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}
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return 0;
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}
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pub const blockdev = kernel.bio.BlockDev{ .read = ide_block_read };
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pub const sectorbuffer = [1]u8{0} ** 512;
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pub fn ide_block_read(lba: u64) void {
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const a = ide_read_sectors(0, 1, lba, 0x8, @ptrToInt(§orbuffer[0]));
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if (a != 0) kernel.println("ide_read_sectors failed {}", a);
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}
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pub fn ide_read_sectors(drive: u2, numsects: u8, lba: u64, es: u8, edi: usize) u8 {
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// 1: Check if the drive presents:
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if (ide_devices[drive].reserved == 0) {
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return 0x1; // Drive Not Found!
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} else if (ide_devices[drive].idetype == IDE_ATA and (lba + numsects) > ide_devices[drive].size) {
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// 2: Check if inputs are valid:
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return 0x2; // Seeking to invalid position.
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} else {
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// 3: Read in PIO Mode through Polling & IRQs:
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var err: u8 = 0;
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if (ide_devices[drive].idetype == IDE_ATA) {
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err = ide_ata_access(ATA_READ, drive, lba, numsects, es, edi);
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} else if (ide_devices[drive].idetype == IDE_ATAPI) {
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var i: u8 = 0;
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while (i < numsects) : (i = i + 1) {
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// err = ide_atapi_read(drive, lba + i, 1, es, edi + (i * 2048));
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}
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}
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// ide_print_error(drive, err);
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return err;
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}
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}
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pub fn init(dev: kernel.pci.PciDevice) void {
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kernel.println("-- ide init --");
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kernel.print("[ide] ");
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dev.format();
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assert(dev.header_type() == 0x0); // mass storage device
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dev.config_write(@intCast(u8, 0xfe), 0x3c);
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if (dev.intr_line() == 0xfe) {
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kernel.println("[ide] detected ATA device");
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} else {
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kernel.println("Potential SATA device, aborting.");
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x86.hang();
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}
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const BAR0 = @intCast(u16, dev.bar(0));
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const BAR1 = @intCast(u16, dev.bar(1));
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const BAR2 = @intCast(u16, dev.bar(2));
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const BAR3 = @intCast(u16, dev.bar(3));
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const BAR4 = @intCast(u16, dev.bar(4));
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channels[ATA_PRIMARY].base = if (BAR0 == 0) 0x1f0 else BAR0;
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channels[ATA_PRIMARY].ctrl = if (BAR1 == 0) 0x3F6 else BAR1;
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channels[ATA_SECONDARY].base = if (BAR2 == 0) 0x170 else BAR2;
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channels[ATA_SECONDARY].ctrl = if (BAR3 == 0) 0x376 else BAR3;
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channels[ATA_PRIMARY].bmide = (BAR4 & 0xFFFC); // Bus Master IDE
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channels[ATA_SECONDARY].bmide = (BAR4 & 0xFFFC) + 8; // Bus Master IDE
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// turn off irqs
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ide_write(ATA_PRIMARY, ATA_REG_CONTROL, 2);
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ide_write(ATA_SECONDARY, ATA_REG_CONTROL, 2);
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// parse identification space
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var count: usize = 0;
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var err: u8 = 0;
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var status: u8 = 0;
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for ([_]u8{ 0, 1 }) |i| {
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for ([_]u8{ 0, 1 }) |j| {
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var idetype: u8 = IDE_ATA;
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ide_devices[count].reserved = 0; // Assuming that no drive here.
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// (I) Select Drive:
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ide_write(i, ATA_REG_HDDEVSEL, 0xA0 | (j << 4)); // Select Drive.
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kernel.task.usleep(1000) catch unreachable; // Wait 1ms for drive select to work.
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// (II) Send ATA Identify Command:
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ide_write(i, ATA_REG_COMMAND, ATA_CMD_IDENTIFY);
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kernel.task.usleep(1000) catch unreachable;
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if (ide_read(i, ATA_REG_STATUS) == 0) continue; // If Status = 0, No Device.
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while (true) {
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status = ide_read(i, ATA_REG_STATUS);
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if (status & ATA_SR_ERR != 0) {
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err = 1;
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break;
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} // If Err, Device is not ATA.
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if ((status & ATA_SR_BSY == 0) and (status & ATA_SR_DRQ != 0)) break; // Everything is right.
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}
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// (IV) Probe for ATAPI Devices:)
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if (err != 0) {
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// Device is not ATA
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const cl = ide_read(i, ATA_REG_LBA1);
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const ch = ide_read(i, ATA_REG_LBA2);
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if (cl == 0x14 and ch == 0xEB) idetype = IDE_ATAPI;
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if (cl == 0x69 and ch == 0x96) idetype = IDE_ATAPI;
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if (idetype != IDE_ATAPI) continue; // Unknown Type (may not be a device).
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ide_write(i, ATA_REG_COMMAND, ATA_CMD_IDENTIFY_PACKET);
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kernel.task.usleep(1000) catch unreachable;
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}
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// (V) Read Identification Space of the Device:
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ide_read_buffer(i, ATA_REG_DATA, &ide_buf, 128);
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ide_devices[count].reserved = 1;
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ide_devices[count].idetype = idetype;
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ide_devices[count].channel = i;
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ide_devices[count].drive = j;
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ide_devices[count].signature = @ptrCast(*const u8, &ide_buf[ATA_IDENT_DEVICETYPE]).*;
|
|
ide_devices[count].capabilities = @ptrCast(*const u8, &ide_buf[ATA_IDENT_CAPABILITIES]).*;
|
|
ide_devices[count].commandsets = @ptrCast(*const usize, &ide_buf[ATA_IDENT_COMMANDSETS]).*;
|
|
|
|
// (VII) Get Size:
|
|
if (ide_devices[count].commandsets & (1 << 26) != 0) {
|
|
// Device uses 48-Bit Addressing:
|
|
ide_devices[count].size = @ptrCast(*const usize, &ide_buf[ATA_IDENT_MAX_LBA_EXT]).*;
|
|
} else {
|
|
// Device uses CHS or 28-bit Addressing:
|
|
ide_devices[count].size = @ptrCast(*const usize, &ide_buf[ATA_IDENT_MAX_LBA]).*;
|
|
}
|
|
|
|
kernel.println("120 {x}", ide_buf[120..122]);
|
|
kernel.println("max_lba = {x}", ide_buf[ATA_IDENT_MAX_LBA .. ATA_IDENT_MAX_LBA + 4]);
|
|
kernel.println("max_lba = {x}", ide_buf[ATA_IDENT_MAX_LBA]);
|
|
kernel.println("max_lba = {x}", ide_buf[ATA_IDENT_MAX_LBA + 1]);
|
|
kernel.println("max_lba = {x}", ide_buf[ATA_IDENT_MAX_LBA + 2]);
|
|
kernel.println("max_lba = {x}", ide_buf[ATA_IDENT_MAX_LBA + 3]);
|
|
kernel.println("max_lba = {}", @ptrCast(*const u8, &ide_buf[ATA_IDENT_MAX_LBA]).*);
|
|
// (VIII) String indicates model of device (like Western Digital HDD and SONY DVD-RW...):
|
|
var k: u16 = 0;
|
|
while (k < 40) : (k = k + 2) {
|
|
ide_devices[count].model[k] = ide_buf[ATA_IDENT_MODEL + k + 1];
|
|
ide_devices[count].model[k + 1] = ide_buf[ATA_IDENT_MODEL + k];
|
|
}
|
|
ide_devices[count].model[40] = 0; // Terminate String.
|
|
|
|
count = count + 1;
|
|
}
|
|
}
|
|
// 4- Print Summary:
|
|
for ([_]u8{ 0, 1, 2, 3 }) |i| {
|
|
if (ide_devices[i].reserved == 1) {
|
|
kernel.println(
|
|
"[ide] drive {} {} ({}GB) - {}",
|
|
i,
|
|
if (ide_devices[i].idetype == 0) "ATA" else "ATAPI",
|
|
ide_devices[i].size,
|
|
ide_devices[i].model,
|
|
);
|
|
}
|
|
}
|
|
}
|