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+ + + + diff --git a/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/ModelAdvisorData b/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/ModelAdvisorData new file mode 100644 index 0000000..58d8fc1 Binary files /dev/null and b/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/ModelAdvisorData differ diff --git a/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/g/ModelAdvisorData b/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/g/ModelAdvisorData new file mode 100644 index 0000000..273b96b Binary files /dev/null and b/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/g/ModelAdvisorData differ diff --git a/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/g/model_diagnose_custom.html b/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/g/model_diagnose_custom.html new file mode 100644 index 0000000..06685d5 --- /dev/null +++ b/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/g/model_diagnose_custom.html @@ -0,0 +1,174 @@ + Model Advisor Report Customization + + + +

Model Advisor Customization

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Help

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Title  Check model for known block upgrade issues
TitleID  mathworks.design.Update
Title  Check rapid accelerator signal logging
TitleID  mathworks.design.CheckRapidAcceleratorSignalLogging
Title  Check get_param calls for block CompiledSampleTime
TitleID  mathworks.design.CallsGetParamCompiledSampleTime
Title  Identify unconnected lines, input ports, and output ports
TitleID  mathworks.design.UnconnectedLinesPorts
Title  Check root model Inport block specifications
TitleID  mathworks.design.RootInportSpec
Title  Check optimization settings
TitleID  mathworks.design.OptimizationSettings
Title  Check for parameter tunability information ignored for referenced models
TitleID  mathworks.design.ParamTunabilityIgnored
Title  Check for implicit signal resolution
TitleID  mathworks.design.ImplicitSignalResolution
Title  Check for optimal bus virtuality
TitleID  mathworks.design.OptBusVirtuality
Title  Check for calls to slDataTypeAndScale()
TitleID  mathworks.design.CallslDataTypeAndScale
Title  Check for Discrete-Time Integrator blocks with initial condition uncertainty
TitleID  mathworks.design.DiscreteTimeIntegratorInitCondition
Title  Identify disabled library links
TitleID  mathworks.design.DisabledLibLinks
Title  Identify parameterized library links
TitleID  mathworks.design.ParameterizedLibLinks
Title  Identify unresolved library links
TitleID  mathworks.design.UnresolvedLibLinks
Title  Identify model reference variants and variant subsystems that override variant choice
TitleID  mathworks.design.VariantOverride
Title  Identify configurable subsystem blocks for converting to variant subsystem blocks
TitleID  mathworks.design.CSStoVSSConvert
Title  Check usage of function-call connections
TitleID  mathworks.design.CheckForProperFcnCallUsage
Title  Check signal logging save format
TitleID  mathworks.design.SigLogSaveFormat
Title  Check and update masked blocks in library to use promoted parameters
TitleID  mathworks.design.CheckAndUpdateOldMaskedBuiltinBlocks
Title  Check and update mask image display commands with unnecessary imread() function calls
TitleID  mathworks.design.CheckMaskDisplayImageFormat
Title  Check and update model to use toolchain approach to build generated code
TitleID  mathworks.codegen.toolchainInfoUpgradeAdvisor.check
Title  Runtime diagnostics for S-functions
TitleID  mathworks.design.DiagnosticSFcn
Title  Check if Read/Write diagnostics are enabled for Data Store blocks
TitleID  mathworks.design.DiagnosticDataStoreBlk
Title  Check Data Store Memory blocks for multitasking, strong typing, and shadowing issues
TitleID  mathworks.design.DataStoreMemoryBlkIssue
Title  Check that the model is saved in SLX format
TitleID  mathworks.design.UseSLXFile
Title  Check model for foreign characters
TitleID  mathworks.design.characterEncoding
Title  Check Model History properties
TitleID  mathworks.design.SLXModelProperties
Title  Identify masked blocks that specify tabs in mask dialog using MaskTabNames parameter
TitleID  mathworks.design.CheckAndUpdateOldMaskTabnames
Title  Check conversion input parameters
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.InputParameters
Title  Check model configurations
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.ModelConfigurations
Title  Check subsystem interface
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.SubsystemInterface
Title  Check subsystem content
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.SubsystemContent
Title  Complete conversion
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.CompleteConversion
Title  Create baseline to measure the performance. The baseline contains the time to run the simulation and the simulation results (signals logged). To create a baseline, configure the model to log states in the workspace and save the signals in 'Structure with time' format.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CreateBaseline
Title  Some diagnostics, such as 'Solver data inconsistency', incur run-time overhead during simulation. To improve simulation speed, disable these diagnostics if they are not necessary.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.IdentifyExpensiveDiagnostics
Title  Some optimizations, such as 'Block reduction', may be disabled. To improve simulation speed, enable these optimization settings.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.IdentifyApplicableOptimizations
Title  Improperly configured lookup table blocks can affect the simulation speed of a model.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.InefficientLookupTableBlocks
Title  Analyze MATLAB System block for code generation capability.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.DetectIntSysObjBlocks
Title  Avoid using Interpreted MATLAB Function blocks.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.DetectIntMATLABFcnBlocks
Title  Disabling debugging on MATLAB Function blocks can improve simulation speed.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckMATLABFcnBlockDebugStatus
Title  Disabling debugging on Stateflow blocks can improve simulation speed.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckStateflowDebugStatus
Title  Disabling simulation target settings, such as 'Echo expression without semicolons', can improve simulation speed.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckSimTargetEchoStatus
Title  Check if model reference rebuild setting is set to the proper value
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckModelRefRebuildSetting
Title  Open the Upgrade Advisor
TitleID  com.mathworks.Simulink.UpgradeAdvisor.MAEntryPoint
Title  Upgrade models in a hierarchy
TitleID  com.mathworks.Simulink.UpgradeAdvisor.UpgradeModelHierarchy
Title  Check for non-continuous signals driving derivative ports
TitleID  mathworks.design.NonContSigDerivPort
Title  Check if model with referenced models can be built in parallel with optimal settings.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckModelRefParallelBuild
Title  Use circular buffer to improve simulation speed for Delay blocks with large states.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckDelayBlockCircularBufferSetting
Title  The selection of an explicit or implicit solver depends on the approximation of the model stiffness at the beginning of the simulation. If the model represents a stiff system, use the ode15s solver. Otherwise, use the ode45 solver.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.SolverTypeSelection
Title  Changing simulation mode can improve simulation speed.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckSimulationModesComparison
Title  Running with compiler optimizations turned on can improve simulation speed.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckSimulationCompilerOptimization
Title  Validate the overall performance improvement in your model using this check. If performance is worse than baseline, Performance Advisor discards all changes and loads the original model.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.FinalValidation
Title  Check model for known block upgrade issues requiring compile time information
TitleID  mathworks.design.UpdateRequireCompile
Title  Check for partial structure parameter usage with bus signals
TitleID  mathworks.design.PartialBusParams
Title  Check bus usage
TitleID  mathworks.design.MuxBlkAsBusCreator
Title  Check for potentially delayed function-call block return values
TitleID  mathworks.design.DelayedFcnCallSubsys
Title  Identify block output signals with continuous sample time and non-floating point data type
TitleID  mathworks.design.OutputSignalSampleTime
Title  Check usage of Merge blocks
TitleID  mathworks.design.MergeBlkUsage
Title  Check consistency of initialization parameters for Outport and Merge blocks
TitleID  mathworks.design.InitParamOutportMergeBlk
Title  Check data store block sample times for modeling errors
TitleID  mathworks.design.DataStoreBlkSampleTime
Title  Check for potential ordering issues involving data store access
TitleID  mathworks.design.OrderingDataStoreAccess
Title  Check for Mux blocks used to create bus signals
TitleID  mathworks.design.CheckMuxUsedAsBusCreatorUpgrade
Title  Check for root outports with constant sample time
TitleID  mathworks.design.CheckConstRootOutportWithInterfaceUpgrade
Title  Identify time-varying source blocks interfering with frequency response estimation
TitleID  mathworks.slcontrolfrest.timevaryingsources
Title  Identify questionable operations for strict single-precision design
TitleID  mathworks.design.StowawayDoubles
Task Name  Simulation Accuracy
Task Name  Simulation Runtime Accuracy Diagnostics
Task Name  Managing Data Store Memory Blocks
Task Name  Simulink Model File Integrity
Task Name  Modeling Signals and Parameters using Buses
Task Name  Code Generation Efficiency
Task Name  Modeling Single-Precision Systems
Task Name  Simulink
Task Name  Library Links
Task Name  Model Referencing
Task Name  Modeling Standards for DO-178C/DO-331
Task Name  Model Referencing
Task Name  Managing Library Links And Variants
Task Name  Upgrading to the Current Simulink Version
Task Name  Frequency Response Estimation
\ No newline at end of file diff --git a/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/g/report.html b/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/g/report.html new file mode 100644 index 0000000..3be0af6 --- /dev/null +++ b/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/g/report.html @@ -0,0 +1,633 @@ + + + + + +Model Advisor Report for 'tipe_model/g' + + + + + + + +
+
+ + + + + + + + + + + + + + + +
+ +Model Advisor Report + + +
+ +Simulink version: 8.3 + + + + +Model version: 1.25 + + +
+ +System: tipe_model/g + + + + +Current run: 21-Mai-2015 16:42:12 + + +
+

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+
+
+ + \ No newline at end of file diff --git a/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/model_diagnose_custom.html b/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/model_diagnose_custom.html new file mode 100644 index 0000000..06685d5 --- /dev/null +++ b/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/model_diagnose_custom.html @@ -0,0 +1,174 @@ + Model Advisor Report Customization + + + +

Model Advisor Customization

+ +

Help

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Title  Check model for known block upgrade issues
TitleID  mathworks.design.Update
Title  Check rapid accelerator signal logging
TitleID  mathworks.design.CheckRapidAcceleratorSignalLogging
Title  Check get_param calls for block CompiledSampleTime
TitleID  mathworks.design.CallsGetParamCompiledSampleTime
Title  Identify unconnected lines, input ports, and output ports
TitleID  mathworks.design.UnconnectedLinesPorts
Title  Check root model Inport block specifications
TitleID  mathworks.design.RootInportSpec
Title  Check optimization settings
TitleID  mathworks.design.OptimizationSettings
Title  Check for parameter tunability information ignored for referenced models
TitleID  mathworks.design.ParamTunabilityIgnored
Title  Check for implicit signal resolution
TitleID  mathworks.design.ImplicitSignalResolution
Title  Check for optimal bus virtuality
TitleID  mathworks.design.OptBusVirtuality
Title  Check for calls to slDataTypeAndScale()
TitleID  mathworks.design.CallslDataTypeAndScale
Title  Check for Discrete-Time Integrator blocks with initial condition uncertainty
TitleID  mathworks.design.DiscreteTimeIntegratorInitCondition
Title  Identify disabled library links
TitleID  mathworks.design.DisabledLibLinks
Title  Identify parameterized library links
TitleID  mathworks.design.ParameterizedLibLinks
Title  Identify unresolved library links
TitleID  mathworks.design.UnresolvedLibLinks
Title  Identify model reference variants and variant subsystems that override variant choice
TitleID  mathworks.design.VariantOverride
Title  Identify configurable subsystem blocks for converting to variant subsystem blocks
TitleID  mathworks.design.CSStoVSSConvert
Title  Check usage of function-call connections
TitleID  mathworks.design.CheckForProperFcnCallUsage
Title  Check signal logging save format
TitleID  mathworks.design.SigLogSaveFormat
Title  Check and update masked blocks in library to use promoted parameters
TitleID  mathworks.design.CheckAndUpdateOldMaskedBuiltinBlocks
Title  Check and update mask image display commands with unnecessary imread() function calls
TitleID  mathworks.design.CheckMaskDisplayImageFormat
Title  Check and update model to use toolchain approach to build generated code
TitleID  mathworks.codegen.toolchainInfoUpgradeAdvisor.check
Title  Runtime diagnostics for S-functions
TitleID  mathworks.design.DiagnosticSFcn
Title  Check if Read/Write diagnostics are enabled for Data Store blocks
TitleID  mathworks.design.DiagnosticDataStoreBlk
Title  Check Data Store Memory blocks for multitasking, strong typing, and shadowing issues
TitleID  mathworks.design.DataStoreMemoryBlkIssue
Title  Check that the model is saved in SLX format
TitleID  mathworks.design.UseSLXFile
Title  Check model for foreign characters
TitleID  mathworks.design.characterEncoding
Title  Check Model History properties
TitleID  mathworks.design.SLXModelProperties
Title  Identify masked blocks that specify tabs in mask dialog using MaskTabNames parameter
TitleID  mathworks.design.CheckAndUpdateOldMaskTabnames
Title  Check conversion input parameters
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.InputParameters
Title  Check model configurations
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.ModelConfigurations
Title  Check subsystem interface
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.SubsystemInterface
Title  Check subsystem content
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.SubsystemContent
Title  Complete conversion
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.CompleteConversion
Title  Create baseline to measure the performance. The baseline contains the time to run the simulation and the simulation results (signals logged). To create a baseline, configure the model to log states in the workspace and save the signals in 'Structure with time' format.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CreateBaseline
Title  Some diagnostics, such as 'Solver data inconsistency', incur run-time overhead during simulation. To improve simulation speed, disable these diagnostics if they are not necessary.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.IdentifyExpensiveDiagnostics
Title  Some optimizations, such as 'Block reduction', may be disabled. To improve simulation speed, enable these optimization settings.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.IdentifyApplicableOptimizations
Title  Improperly configured lookup table blocks can affect the simulation speed of a model.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.InefficientLookupTableBlocks
Title  Analyze MATLAB System block for code generation capability.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.DetectIntSysObjBlocks
Title  Avoid using Interpreted MATLAB Function blocks.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.DetectIntMATLABFcnBlocks
Title  Disabling debugging on MATLAB Function blocks can improve simulation speed.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckMATLABFcnBlockDebugStatus
Title  Disabling debugging on Stateflow blocks can improve simulation speed.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckStateflowDebugStatus
Title  Disabling simulation target settings, such as 'Echo expression without semicolons', can improve simulation speed.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckSimTargetEchoStatus
Title  Check if model reference rebuild setting is set to the proper value
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckModelRefRebuildSetting
Title  Open the Upgrade Advisor
TitleID  com.mathworks.Simulink.UpgradeAdvisor.MAEntryPoint
Title  Upgrade models in a hierarchy
TitleID  com.mathworks.Simulink.UpgradeAdvisor.UpgradeModelHierarchy
Title  Check for non-continuous signals driving derivative ports
TitleID  mathworks.design.NonContSigDerivPort
Title  Check if model with referenced models can be built in parallel with optimal settings.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckModelRefParallelBuild
Title  Use circular buffer to improve simulation speed for Delay blocks with large states.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckDelayBlockCircularBufferSetting
Title  The selection of an explicit or implicit solver depends on the approximation of the model stiffness at the beginning of the simulation. If the model represents a stiff system, use the ode15s solver. Otherwise, use the ode45 solver.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.SolverTypeSelection
Title  Changing simulation mode can improve simulation speed.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckSimulationModesComparison
Title  Running with compiler optimizations turned on can improve simulation speed.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckSimulationCompilerOptimization
Title  Validate the overall performance improvement in your model using this check. If performance is worse than baseline, Performance Advisor discards all changes and loads the original model.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.FinalValidation
Title  Check model for known block upgrade issues requiring compile time information
TitleID  mathworks.design.UpdateRequireCompile
Title  Check for partial structure parameter usage with bus signals
TitleID  mathworks.design.PartialBusParams
Title  Check bus usage
TitleID  mathworks.design.MuxBlkAsBusCreator
Title  Check for potentially delayed function-call block return values
TitleID  mathworks.design.DelayedFcnCallSubsys
Title  Identify block output signals with continuous sample time and non-floating point data type
TitleID  mathworks.design.OutputSignalSampleTime
Title  Check usage of Merge blocks
TitleID  mathworks.design.MergeBlkUsage
Title  Check consistency of initialization parameters for Outport and Merge blocks
TitleID  mathworks.design.InitParamOutportMergeBlk
Title  Check data store block sample times for modeling errors
TitleID  mathworks.design.DataStoreBlkSampleTime
Title  Check for potential ordering issues involving data store access
TitleID  mathworks.design.OrderingDataStoreAccess
Title  Check for Mux blocks used to create bus signals
TitleID  mathworks.design.CheckMuxUsedAsBusCreatorUpgrade
Title  Check for root outports with constant sample time
TitleID  mathworks.design.CheckConstRootOutportWithInterfaceUpgrade
Title  Identify time-varying source blocks interfering with frequency response estimation
TitleID  mathworks.slcontrolfrest.timevaryingsources
Title  Identify questionable operations for strict single-precision design
TitleID  mathworks.design.StowawayDoubles
Task Name  Simulation Accuracy
Task Name  Simulation Runtime Accuracy Diagnostics
Task Name  Managing Data Store Memory Blocks
Task Name  Simulink Model File Integrity
Task Name  Modeling Signals and Parameters using Buses
Task Name  Code Generation Efficiency
Task Name  Modeling Single-Precision Systems
Task Name  Simulink
Task Name  Library Links
Task Name  Model Referencing
Task Name  Modeling Standards for DO-178C/DO-331
Task Name  Model Referencing
Task Name  Managing Library Links And Variants
Task Name  Upgrading to the Current Simulink Version
Task Name  Frequency Response Estimation
\ No newline at end of file diff --git a/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/report.html b/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/report.html new file mode 100644 index 0000000..2fdb7b3 --- /dev/null +++ b/Simulation (matlab simulink)/slprj/modeladvisor/tipe__model/report.html @@ -0,0 +1,633 @@ + + + + + +Model Advisor Report for 'tipe_model' + + + + + + + +
+
+ + + + + + + + + + + + + + + +
+ +Model Advisor Report + + +
+ +Simulink version: 8.3 + + + + +Model version: 1.25 + + +
+ +System: tipe_model + + + + +Current run: 21-Mai-2015 16:42:20 + + +
+

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+
+
+ + \ No newline at end of file diff --git a/Simulation (matlab simulink)/slprj/sl_proj.tmw b/Simulation (matlab simulink)/slprj/sl_proj.tmw new file mode 100644 index 0000000..10a7474 --- /dev/null +++ b/Simulation (matlab simulink)/slprj/sl_proj.tmw @@ -0,0 +1,2 @@ +Simulink Coder project marker file. Please don't change it. +slprjVersion: 8.3_50_013 \ No newline at end of file diff --git a/Simulation (matlab simulink)/sp_array.slx b/Simulation (matlab simulink)/sp_array.slx new file mode 100644 index 0000000..15e3643 Binary files /dev/null and b/Simulation (matlab simulink)/sp_array.slx differ diff --git a/Simulation (matlab simulink)/speed.png b/Simulation (matlab simulink)/speed.png new file mode 100644 index 0000000..61f8ab9 Binary files /dev/null and b/Simulation (matlab simulink)/speed.png differ diff --git a/Simulation (matlab simulink)/tipe_gauss.prj b/Simulation (matlab simulink)/tipe_gauss.prj new file mode 100755 index 0000000..c0d83ce --- /dev/null +++ b/Simulation (matlab simulink)/tipe_gauss.prj @@ -0,0 +1,7 @@ + + + + This is a Simulink Project + + + diff --git a/Simulation (matlab simulink)/tipe_model.mdl b/Simulation (matlab simulink)/tipe_model.mdl new file mode 100644 index 0000000..2bb20ed --- /dev/null +++ b/Simulation (matlab simulink)/tipe_model.mdl @@ -0,0 +1,4058 @@ +Model { + Name "tipe_model" + Version 8.3 + MdlSubVersion 0 + SavedCharacterEncoding "ISO-8859-1" + GraphicalInterface { + NumRootInports 0 + NumRootOutports 0 + ParameterArgumentNames "" + ComputedModelVersion "1.30" + NumModelReferences 0 + NumTestPointedSignals 0 + } + SaveDefaultBlockParams on + ScopeRefreshTime 0.035000 + OverrideScopeRefreshTime on + DisableAllScopes off + DataTypeOverride "UseLocalSettings" + DataTypeOverrideAppliesTo "AllNumericTypes" + MinMaxOverflowLogging "UseLocalSettings" + MinMaxOverflowArchiveMode "Overwrite" + FPTRunName "Run 1" + MaxMDLFileLineLength 120 + Object { + $PropName "BdWindowsInfo" + $ObjectID 1 + $ClassName "Simulink.BDWindowsInfo" + Object { + $PropName "WindowsInfo" + $ObjectID 2 + $ClassName "Simulink.WindowInfo" + IsActive [1] + Location [0.0, 23.0, 1440.0, 873.0] + Object { + $PropName "ModelBrowserInfo" + $ObjectID 3 + $ClassName "Simulink.ModelBrowserInfo" + Visible [0] + DockPosition "Left" + Width [50] + Height [50] + Filter [9] + } + Object { + $PropName "ExplorerBarInfo" + $ObjectID 4 + $ClassName "Simulink.ExplorerBarInfo" + Visible [1] + } + Object { + $PropName "EditorsInfo" + $ObjectID 5 + $ClassName "Simulink.EditorInfo" + IsActive [1] + ViewObjType "SimulinkTopLevel" + LoadSaveID "0" + Extents [1406.0, 703.0] + ZoomFactor [2.5] + Offset [-18.716828703703726, 114.96296296296295] + } + } + } + Created "Sat Dec 20 18:36:45 2014" + Creator "jackhalford" + UpdateHistory "UpdateHistoryNever" + ModifiedByFormat "%" + LastModifiedBy "jackhalford" + ModifiedDateFormat "%" + LastModifiedDate "Wed Jun 03 17:47:44 2015" + RTWModifiedTimeStamp 355251001 + ModelVersionFormat "1.%" + ConfigurationManager "none" + SampleTimeColors off + SampleTimeAnnotations off + LibraryLinkDisplay "disabled" + WideLines off + ShowLineDimensions off + ShowPortDataTypes off + ShowDesignRanges off + ShowLoopsOnError on + IgnoreBidirectionalLines off + ShowStorageClass off + ShowTestPointIcons on + ShowSignalResolutionIcons on + ShowViewerIcons on + SortedOrder off + ExecutionContextIcon off + ShowLinearizationAnnotations on + BlockNameDataTip off + BlockParametersDataTip off + BlockDescriptionStringDataTip off + ToolBar on + StatusBar on + BrowserShowLibraryLinks off + BrowserLookUnderMasks off + SimulationMode "normal" + PauseTimes "5" + NumberOfSteps 1 + SnapshotBufferSize 10 + SnapshotInterval 10 + NumberOfLastSnapshots 0 + LinearizationMsg "none" + Profile off + ParamWorkspaceSource "MATLABWorkspace" + AccelSystemTargetFile "accel.tlc" + AccelTemplateMakefile "accel_default_tmf" + AccelMakeCommand "make_rtw" + TryForcingSFcnDF off + Object { + $PropName "DataLoggingOverride" + $ObjectID 6 + $ClassName "Simulink.SimulationData.ModelLoggingInfo" + model_ "tipe_model" + signals_ [] + overrideMode_ [0.0] + Array { + Type "Cell" + Dimension 1 + Cell "tipe_model" + PropName "logAsSpecifiedByModels_" + } + Array { + Type "Cell" + Dimension 1 + Cell [] + PropName "logAsSpecifiedByModelsSSIDs_" + } + } + RecordCoverage off + CovPath "/" + CovSaveName "covdata" + CovMetricSettings "dw" + CovNameIncrementing off + CovHtmlReporting on + CovForceBlockReductionOff on + CovEnableCumulative on + covSaveCumulativeToWorkspaceVar on + CovSaveSingleToWorkspaceVar on + CovCumulativeVarName "covCumulativeData" + CovCumulativeReport off + CovReportOnPause on + CovModelRefEnable "Off" + CovExternalEMLEnable off + CovSFcnEnable off + CovBoundaryAbsTol 0.000010 + CovBoundaryRelTol 0.010000 + ExtModeBatchMode off + ExtModeEnableFloating on + ExtModeTrigType "manual" + ExtModeTrigMode "normal" + ExtModeTrigPort "1" + ExtModeTrigElement "any" + ExtModeTrigDuration 1000 + ExtModeTrigDurationFloating "auto" + ExtModeTrigHoldOff 0 + ExtModeTrigDelay 0 + ExtModeTrigDirection "rising" + ExtModeTrigLevel 0 + ExtModeArchiveMode "off" + ExtModeAutoIncOneShot off + ExtModeIncDirWhenArm off + ExtModeAddSuffixToVar off + ExtModeWriteAllDataToWs off + ExtModeArmWhenConnect on + ExtModeSkipDownloadWhenConnect off + ExtModeLogAll on + ExtModeAutoUpdateStatusClock on + BufferReuse on + ShowModelReferenceBlockVersion off + ShowModelReferenceBlockIO off + Array { + Type "Handle" + Dimension 1 + Simulink.ConfigSet { + $ObjectID 7 + Version "1.14.2" + Array { + Type "Handle" + Dimension 8 + Simulink.SolverCC { + $ObjectID 8 + Version "1.14.2" + StartTime "0" + StopTime "0.03" + AbsTol "auto" + FixedStep "10-6" + InitialStep "auto" + MaxNumMinSteps "-1" + MaxOrder 5 + ZcThreshold "auto" + ConsecutiveZCsStepRelTol "10*128*eps" + MaxConsecutiveZCs "1000" + ExtrapolationOrder 4 + NumberNewtonIterations 1 + MaxStep "1e-6" + MinStep "auto" + MaxConsecutiveMinStep "1" + RelTol "1e-3" + SolverMode "Auto" + EnableConcurrentExecution off + ConcurrentTasks off + Solver "ode113" + SolverName "ode113" + SolverJacobianMethodControl "auto" + ShapePreserveControl "EnableAll" + ZeroCrossControl "UseLocalSettings" + ZeroCrossAlgorithm "Nonadaptive" + AlgebraicLoopSolver "TrustRegion" + SolverResetMethod "Fast" + PositivePriorityOrder off + AutoInsertRateTranBlk off + SampleTimeConstraint "Unconstrained" + InsertRTBMode "Whenever possible" + } + Simulink.DataIOCC { + $ObjectID 9 + Version "1.14.2" + Decimation "1" + ExternalInput "[t, u]" + FinalStateName "xFinal" + InitialState "xInitial" + LimitDataPoints on + MaxDataPoints "1000" + LoadExternalInput off + LoadInitialState off + SaveFinalState off + SaveCompleteFinalSimState off + SaveFormat "Array" + SignalLoggingSaveFormat "Dataset" + SaveOutput on + SaveState off + SignalLogging on + DSMLogging on + InspectSignalLogs off + VisualizeSimOutput on + SaveTime on + ReturnWorkspaceOutputs off + StateSaveName "xout" + TimeSaveName "tout" + OutputSaveName "yout" + SignalLoggingName "logsout" + DSMLoggingName "dsmout" + OutputOption "RefineOutputTimes" + OutputTimes "[]" + ReturnWorkspaceOutputsName "out" + Refine "1" + } + Simulink.OptimizationCC { + $ObjectID 10 + Version "1.14.2" + Array { + Type "Cell" + Dimension 8 + Cell "BooleansAsBitfields" + Cell "PassReuseOutputArgsAs" + Cell "PassReuseOutputArgsThreshold" + Cell "ZeroExternalMemoryAtStartup" + Cell "ZeroInternalMemoryAtStartup" + Cell "OptimizeModelRefInitCode" + Cell "NoFixptDivByZeroProtection" + Cell "UseSpecifiedMinMax" + PropName "DisabledProps" + } + BlockReduction on + BooleanDataType on + ConditionallyExecuteInputs on + InlineParams off + UseIntDivNetSlope off + UseFloatMulNetSlope off + DefaultUnderspecifiedDataType "double" + UseSpecifiedMinMax off + InlineInvariantSignals off + OptimizeBlockIOStorage on + BufferReuse on + EnhancedBackFolding off + CachingGlobalReferences off + GlobalBufferReuse on + StrengthReduction off + ExpressionFolding on + BooleansAsBitfields off + BitfieldContainerType "uint_T" + EnableMemcpy on + MemcpyThreshold 64 + PassReuseOutputArgsAs "Structure reference" + ExpressionDepthLimit 128 + FoldNonRolledExpr on + LocalBlockOutputs on + RollThreshold 5 + SystemCodeInlineAuto off + StateBitsets off + DataBitsets off + ActiveStateOutputEnumStorageType "Native Integer" + UseTempVars off + ZeroExternalMemoryAtStartup on + ZeroInternalMemoryAtStartup on + InitFltsAndDblsToZero off + NoFixptDivByZeroProtection off + EfficientFloat2IntCast off + EfficientMapNaN2IntZero on + OptimizeModelRefInitCode off + LifeSpan "inf" + MaxStackSize "Inherit from target" + BufferReusableBoundary on + SimCompilerOptimization "Off" + AccelVerboseBuild off + ParallelExecutionInRapidAccelerator on + } + Simulink.DebuggingCC { + $ObjectID 11 + Version "1.14.2" + RTPrefix "error" + ConsistencyChecking "none" + ArrayBoundsChecking "none" + SignalInfNanChecking "none" + SignalRangeChecking "none" + ReadBeforeWriteMsg "UseLocalSettings" + WriteAfterWriteMsg "UseLocalSettings" + WriteAfterReadMsg "UseLocalSettings" + AlgebraicLoopMsg "warning" + ArtificialAlgebraicLoopMsg "warning" + SaveWithDisabledLinksMsg "warning" + SaveWithParameterizedLinksMsg "warning" + CheckSSInitialOutputMsg on + UnderspecifiedInitializationDetection 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"Undefined" + ProdEndianess "Unspecified" + ProdWordSize 32 + ProdShiftRightIntArith on + ProdLongLongMode off + ProdHWDeviceType "32-bit Generic" + TargetBitPerChar 8 + TargetBitPerShort 16 + TargetBitPerInt 32 + TargetBitPerLong 32 + TargetBitPerLongLong 64 + TargetBitPerFloat 32 + TargetBitPerDouble 64 + TargetBitPerPointer 32 + TargetLargestAtomicInteger "Char" + TargetLargestAtomicFloat "None" + TargetShiftRightIntArith on + TargetLongLongMode off + TargetIntDivRoundTo "Undefined" + TargetEndianess "Unspecified" + TargetWordSize 32 + TargetTypeEmulationWarnSuppressLevel 0 + TargetPreprocMaxBitsSint 32 + TargetPreprocMaxBitsUint 32 + TargetHWDeviceType "Specified" + TargetUnknown off + ProdEqTarget on + } + Simulink.ModelReferenceCC { + $ObjectID 13 + Version "1.14.2" + UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" + CheckModelReferenceTargetMessage "error" + EnableParallelModelReferenceBuilds off + ParallelModelReferenceErrorOnInvalidPool on + ParallelModelReferenceMATLABWorkerInit "None" + ModelReferenceNumInstancesAllowed "Multi" + PropagateVarSize "Infer from blocks in model" + ModelReferencePassRootInputsByReference on + ModelReferenceMinAlgLoopOccurrences off + PropagateSignalLabelsOutOfModel off + SupportModelReferenceSimTargetCustomCode off + } + Simulink.SFSimCC { + $ObjectID 14 + Version "1.14.2" + SFSimEnableDebug on + SFSimOverflowDetection on + SFSimEcho on + SimBlas on + SimCtrlC on + SimExtrinsic on + SimIntegrity on + SimUseLocalCustomCode off + SimParseCustomCode on + SimBuildMode "sf_incremental_build" + SimGenImportedTypeDefs off + } + Simulink.RTWCC { + $BackupClass "Simulink.RTWCC" + $ObjectID 15 + Version "1.14.2" + Array { + Type "Cell" + Dimension 15 + Cell "IncludeHyperlinkInReport" + Cell "GenerateTraceInfo" + Cell "GenerateTraceReport" + Cell "GenerateTraceReportSl" + Cell "GenerateTraceReportSf" + Cell "GenerateTraceReportEml" + Cell "PortableWordSizes" + Cell "GenerateWebview" + Cell "GenerateCodeMetricsReport" + Cell "GenerateCodeReplacementReport" + Cell "GenerateErtSFunction" + Cell "CreateSILPILBlock" + Cell "CodeExecutionProfiling" + Cell "CodeProfilingSaveOptions" + Cell "CodeProfilingInstrumentation" + PropName "DisabledProps" + } + SystemTargetFile "grt.tlc" + TLCOptions "" + GenCodeOnly off + MakeCommand "make_rtw" + GenerateMakefile on + PackageGeneratedCodeAndArtifacts off + PackageName "" + TemplateMakefile "grt_default_tmf" + PostCodeGenCommand "" + Description "" + GenerateReport off + SaveLog off + RTWVerbose on + RetainRTWFile off + ProfileTLC off + TLCDebug off + TLCCoverage off + TLCAssert off + ProcessScriptMode "Default" + ConfigurationMode "Optimized" + ProcessScript "" + ConfigurationScript "" + ConfigAtBuild off + RTWUseLocalCustomCode off + RTWUseSimCustomCode off + CustomSourceCode "" + CustomHeaderCode "" + CustomInclude "" + CustomSource "" + CustomLibrary "" + CustomInitializer "" + CustomTerminator "" + Toolchain "Automatically locate an installed toolchain" + BuildConfiguration "Faster Builds" + IncludeHyperlinkInReport off + LaunchReport off + PortableWordSizes off + CreateSILPILBlock "None" + CodeExecutionProfiling off + CodeExecutionProfileVariable "executionProfile" + CodeProfilingSaveOptions "SummaryOnly" + CodeProfilingInstrumentation off + SILDebugging off + TargetLang "C" + IncludeBusHierarchyInRTWFileBlockHierarchyMap off + IncludeERTFirstTime off + GenerateTraceInfo off + GenerateTraceReport off + GenerateTraceReportSl off + GenerateTraceReportSf off + GenerateTraceReportEml off + GenerateCodeInfo off + GenerateWebview off + GenerateCodeMetricsReport off + GenerateCodeReplacementReport off + RTWCompilerOptimization "Off" + RTWCustomCompilerOptimizations "" + CheckMdlBeforeBuild "Off" + CustomRebuildMode "OnUpdate" + DataInitializer "" + SharedConstantsCachingThreshold 1024 + Array { + Type "Handle" + Dimension 2 + Simulink.CodeAppCC { + $ObjectID 16 + Version "1.14.2" + Array { + Type "Cell" + Dimension 23 + Cell "IgnoreCustomStorageClasses" + Cell "IgnoreTestpoints" + Cell "InsertBlockDesc" + Cell "InsertPolySpaceComments" + Cell "SFDataObjDesc" + Cell "MATLABFcnDesc" + Cell "SimulinkDataObjDesc" + Cell "DefineNamingRule" + Cell "SignalNamingRule" + Cell "ParamNamingRule" + Cell "InternalIdentifier" + Cell "InlinedPrmAccess" + Cell "CustomSymbolStr" + Cell "CustomSymbolStrGlobalVar" + Cell "CustomSymbolStrType" + Cell "CustomSymbolStrField" + Cell "CustomSymbolStrFcn" + Cell "CustomSymbolStrFcnArg" + Cell "CustomSymbolStrBlkIO" + Cell "CustomSymbolStrTmpVar" + Cell "CustomSymbolStrMacro" + Cell "CustomSymbolStrUtil" + Cell "ReqsInCode" + PropName "DisabledProps" + } + ForceParamTrailComments off + GenerateComments on + CommentStyle "Auto" + IgnoreCustomStorageClasses on + IgnoreTestpoints off + IncHierarchyInIds off + MaxIdLength 31 + PreserveName off + PreserveNameWithParent off + ShowEliminatedStatement off + OperatorAnnotations off + IncAutoGenComments off + SimulinkDataObjDesc off + SFDataObjDesc off + MATLABFcnDesc off + IncDataTypeInIds off + MangleLength 1 + CustomSymbolStrGlobalVar "$R$N$M" + CustomSymbolStrType "$N$R$M_T" + CustomSymbolStrField "$N$M" + CustomSymbolStrFcn "$R$N$M$F" + CustomSymbolStrFcnArg "rt$I$N$M" + CustomSymbolStrBlkIO "rtb_$N$M" + CustomSymbolStrTmpVar "$N$M" + CustomSymbolStrMacro "$R$N$M" + CustomSymbolStrUtil "$N$C" + DefineNamingRule "None" + ParamNamingRule "None" + SignalNamingRule "None" + InsertBlockDesc off + InsertPolySpaceComments off + SimulinkBlockComments on + MATLABSourceComments off + EnableCustomComments off + InternalIdentifier "Shortened" + InlinedPrmAccess "Literals" + ReqsInCode off + UseSimReservedNames off + } + Simulink.GRTTargetCC { + $BackupClass "Simulink.TargetCC" + $ObjectID 17 + Version "1.14.2" + Array { + Type "Cell" + Dimension 14 + Cell "GeneratePreprocessorConditionals" + Cell "IncludeMdlTerminateFcn" + Cell "CombineOutputUpdateFcns" + Cell "SuppressErrorStatus" + Cell "ERTCustomFileBanners" + Cell "GenerateSampleERTMain" + Cell "GenerateTestInterfaces" + Cell "ModelStepFunctionPrototypeControlCompliant" + Cell "GenerateAllocFcn" + Cell "PurelyIntegerCode" + Cell "SupportComplex" + Cell "SupportAbsoluteTime" + Cell "SupportContinuousTime" + Cell "SupportNonInlinedSFcns" + PropName "DisabledProps" + } + TargetFcnLib "ansi_tfl_table_tmw.mat" + TargetLibSuffix "" + TargetPreCompLibLocation "" + GenFloatMathFcnCalls "NOT IN USE" + TargetLangStandard "C89/C90 (ANSI)" + CodeReplacementLibrary "None" + UtilityFuncGeneration "Auto" + ERTMultiwordTypeDef "System defined" + ERTMultiwordLength 256 + MultiwordLength 2048 + GenerateFullHeader on + GenerateSampleERTMain off + GenerateTestInterfaces off + ModelReferenceCompliant on + ParMdlRefBuildCompliant on + CompOptLevelCompliant on + ConcurrentExecutionCompliant on + IncludeMdlTerminateFcn on + GeneratePreprocessorConditionals "Disable all" + CombineOutputUpdateFcns on + CombineSignalStateStructs off + SuppressErrorStatus off + ERTFirstTimeCompliant off + IncludeFileDelimiter "Auto" + ERTCustomFileBanners off + SupportAbsoluteTime on + LogVarNameModifier "rt_" + MatFileLogging on + MultiInstanceERTCode off + CodeInterfacePackaging "Nonreusable function" + SupportNonFinite on + SupportComplex on + PurelyIntegerCode off + SupportContinuousTime on + SupportNonInlinedSFcns on + SupportVariableSizeSignals off + EnableShiftOperators on + ParenthesesLevel "Nominal" + MATLABClassNameForMDSCustomization "Simulink.SoftwareTarget.GRTCustomization" + ModelStepFunctionPrototypeControlCompliant off + CPPClassGenCompliant on + AutosarCompliant off + GRTInterface off + GenerateAllocFcn off + UseMalloc off + ExtMode off + ExtModeStaticAlloc off + ExtModeTesting off + ExtModeStaticAllocSize 1000000 + ExtModeTransport 0 + ExtModeMexFile "ext_comm" + ExtModeIntrfLevel "Level1" + RTWCAPISignals off + RTWCAPIParams off + RTWCAPIStates off + RTWCAPIRootIO off + GenerateASAP2 off + MultiInstanceErrorCode "Error" + } + PropName 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BlockRotation 270 + BlockMirror on + ShowName off + Inputs "**" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Multiply2" + SID "406" + Ports [2, 1] + Position [115, 147, 145, 178] + ZOrder 178 + ShowName off + Inputs "/*" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + Port { + PortNumber 1 + Name "Uc''(t)" + RTWStorageClass "Auto" + DataLoggingNameMode "SignalName" + } + } + Block { + BlockType Product + Name "Product" + SID "710" + Ports [2, 1] + Position [345, 322, 375, 353] + ZOrder 236 + BlockMirror on + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Saturate + Name "Sat" + SID "407" + Ports [1, 1] + Position [310, 150, 340, 180] + ZOrder 187 + InputPortMap "u0" + UpperLimit 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BlockType Gain + Name "capac1" + SID "638" + Position [405, 124, 425, 146] + ZOrder 222 + ShowName off + Gain "C" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "capacit" + SID "402" + Position [260, 218, 290, 242] + ZOrder 174 + BlockMirror on + ShowName off + Gain "1/C" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "capacit1" + SID "1615" + Position [135, 198, 165, 222] + ZOrder 281 + BlockMirror on + ShowName off + Gain "R" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK" + SID "709" + Position [390, 321, 415, 339] + ZOrder 235 + BlockMirror on + ShowName off + Gain "K*4*10^8" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Scope + Name "f(t)" + SID "642" + Ports [1] + Position [395, 221, 415, 239] + ZOrder 226 + BlockMirror on + BackgroundColor "orange" + Floating off + Location [1, 72, 1441, 895] + Open off + NumInputPorts "1" + ZoomMode "xonly" + List { + ListType AxesTitles + axes1 "%" + } + List { + ListType ScopeGraphics + FigureColor "[0.5 0.5 0.5]" + AxesColor "[0 0 0]" + AxesTickColor "[1 1 1]" + LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" + LineStyles "-|-|-|-|-|-" + LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" + MarkerStyles "none|none|none|none|none|none" + } + ShowLegends off + TimeRange "0.005" + YMin "0" + YMax "80" + SaveName "ScopeData6" + LimitDataPoints off + } + Block { + BlockType SubSystem + Name "g" + SID "650" + Ports [1, 1] + Position [280, 364, 320, 386] + ZOrder 234 + BackgroundColor "magenta" + ShowName off + RequestExecContextInheritance off + System { + Name "g" + Location [0, 23, 1440, 896] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "276" + Block { + BlockType Inport + Name "z\n" + SID "651" + Position [65, 203, 95, 217] + ZOrder -1 + IconDisplay "Port number" + } + Block { + BlockType Sum + Name "Add" + SID "774" + Ports [2, 1] + Position [210, 62, 240, 93] + ZOrder 241 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add1" + SID "776" + Ports [2, 1] + Position [365, 37, 395, 68] + ZOrder 243 + ShowName off + Inputs "+-" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add2" + SID "900" + Ports [2, 1] + Position [315, 27, 345, 58] + ZOrder 267 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add3" + SID "901" + Ports [2, 1] + Position [210, 117, 240, 148] + ZOrder 268 + ShowName off + Inputs "-+" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Constant + Name "Constant1" + SID "775" + Position [235, 14, 285, 26] + ZOrder 242 + ShowName off + Value "4*Rbob^2" + } + Block { + BlockType Constant + Name "Constant4" + SID "899" + Position [145, 57, 185, 73] + ZOrder 266 + ShowName off + Value "4" + } + Block { + BlockType Constant + Name "Constant5" + SID "902" + Position [145, 112, 185, 128] + ZOrder 269 + ShowName off + Value "4" + } + Block { + BlockType Product + Name "Divide" + SID "784" + Ports [2, 1] + Position [490, 47, 520, 78] + ZOrder 248 + Inputs "*/" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Product + Name "Product" + SID "770" + Ports [3, 1] + Position [265, 34, 295, 66] + ZOrder 237 + ShowName off + Inputs "3" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK" + SID "1059" + Position [275, 121, 325, 149] + ZOrder 273 + ShowName off + Gain "Lbob^2" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK1" + SID "1061" + Position [410, 36, 475, 74] + ZOrder 275 + ShowName off + Gain "-4*Rbob^3" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType SubSystem + Name "denom" + SID "946" + Ports [1, 1] + Position [175, 193, 230, 227] + ZOrder 271 + BackgroundColor "magenta" + RequestExecContextInheritance off + System { + Name "denom" + Location [0, 23, 1440, 896] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "612" + Block { + BlockType Inport + Name "z\n" + SID "947" + Position [580, 583, 610, 597] + ZOrder -1 + IconDisplay "Port number" + } + Block { + BlockType SubSystem + Name "M+" + SID "963" + Ports [1, 1] + Position [635, 573, 690, 607] + ZOrder 271 + BackgroundColor "magenta" + RequestExecContextInheritance off + System { + Name "M+" + Location [0, 23, 1440, 896] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "399" + Block { + BlockType Inport + Name "z\n" + SID "964" + Position [480, 378, 510, 392] + ZOrder -1 + IconDisplay "Port number" + } + Block { + BlockType Sum + Name "Add1" + SID "966" + Ports [2, 1] + Position [735, 347, 765, 378] + ZOrder 269 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add2" + SID "967" + Ports [2, 1] + Position [605, 387, 635, 418] + ZOrder 264 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add3" + SID "968" + Ports [2, 1] + Position [680, 337, 710, 368] + ZOrder 267 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Constant + Name "Constant3" + SID "969" + Position [620, 367, 655, 383] + ZOrder 259 + ShowName off + Value "Lbob^2" + } + Block { + BlockType Constant + Name "Constant4" + SID "970" + Position [540, 422, 575, 438] + ZOrder 260 + ShowName off + Value "Rbob^2" + } + Block { + BlockType Product + Name "Product4" + SID "973" + Ports [2, 1] + Position [555, 377, 585, 408] + ZOrder 263 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK" + SID "1062" + Position [650, 391, 700, 419] + ZOrder 274 + ShowName off + Gain "4" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK1" + SID "1063" + Position [595, 331, 645, 359] + ZOrder 275 + ShowName off + Gain "4*Lbob" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "p(z)" + SID "976" + Position [795, 358, 825, 372] + ZOrder -2 + IconDisplay "Port number" + } + Line { + ZOrder 4 + SrcBlock "Product4" + SrcPort 1 + DstBlock "Add2" + DstPort 1 + } + Line { + ZOrder 5 + SrcBlock "Constant4" + SrcPort 1 + Points [10, 0] + DstBlock "Add2" + DstPort 2 + } + Line { + ZOrder 16 + SrcBlock "Add2" + SrcPort 1 + DstBlock "constK" + DstPort 1 + } + Line { + ZOrder 18 + SrcBlock "constK1" + SrcPort 1 + DstBlock "Add3" + DstPort 1 + } + Line { + ZOrder 10 + SrcBlock "Constant3" + SrcPort 1 + Points [5, 0] + DstBlock "Add3" + DstPort 2 + } + Line { + ZOrder 1 + SrcBlock "z\n" + SrcPort 1 + Points [21, 0] + Branch { + ZOrder 19 + Points [0, -40] + DstBlock "constK1" + DstPort 1 + } + Branch { + ZOrder 2 + Points [0, 15] + DstBlock "Product4" + DstPort 2 + } + Branch { + ZOrder 3 + DstBlock "Product4" + DstPort 1 + } + } + Line { + ZOrder 12 + SrcBlock "Add3" + SrcPort 1 + DstBlock "Add1" + DstPort 1 + } + Line { + ZOrder 17 + SrcBlock "constK" + SrcPort 1 + Points [15, 0] + DstBlock "Add1" + DstPort 2 + } + Line { + ZOrder 14 + SrcBlock "Add1" + SrcPort 1 + DstBlock "p(z)" + DstPort 1 + } + } + } + Block { + BlockType SubSystem + Name "M-" + SID "1064" + Ports [1, 1] + Position [635, 628, 690, 662] + ZOrder 276 + BackgroundColor "magenta" + RequestExecContextInheritance off + System { + Name "M-" + Location [0, 23, 1440, 896] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "399" + Block { + BlockType Inport + Name "z\n" + SID "1065" + Position [480, 378, 510, 392] + ZOrder -1 + IconDisplay "Port number" + } + Block { + BlockType Sum + Name "Add1" + SID "1066" + Ports [2, 1] + Position [735, 347, 765, 378] + ZOrder 269 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add2" + SID "1067" + Ports [2, 1] + Position [605, 387, 635, 418] + ZOrder 264 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add3" + SID "1068" + Ports [2, 1] + Position [680, 337, 710, 368] + ZOrder 267 + ShowName off + Inputs "-+" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Constant + Name "Constant3" + SID "1069" + Position [620, 367, 655, 383] + ZOrder 259 + ShowName off + Value "Lbob^2" + } + Block { + BlockType Constant + Name "Constant4" + SID "1070" + Position [540, 422, 575, 438] + ZOrder 260 + ShowName off + Value "Rbob^2" + } + Block { + BlockType Product + Name "Product4" + SID "1071" + Ports [2, 1] + Position [555, 377, 585, 408] + ZOrder 263 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK" + SID "1072" + Position [650, 391, 700, 419] + ZOrder 274 + ShowName off + Gain "4" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK1" + SID "1073" + Position [595, 331, 645, 359] + ZOrder 275 + ShowName off + Gain "4*Lbob" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "p(z)" + SID "1074" + Position [795, 358, 825, 372] + ZOrder -2 + IconDisplay "Port number" + } + Line { + ZOrder 1 + SrcBlock "Product4" + SrcPort 1 + DstBlock "Add2" + DstPort 1 + } + Line { + ZOrder 2 + SrcBlock "Constant4" + SrcPort 1 + Points [10, 0] + DstBlock "Add2" + DstPort 2 + } + Line { + ZOrder 3 + SrcBlock "Add2" + SrcPort 1 + DstBlock "constK" + DstPort 1 + } + Line { + ZOrder 4 + SrcBlock "constK1" + SrcPort 1 + DstBlock "Add3" + DstPort 1 + } + Line { + ZOrder 5 + SrcBlock "Constant3" + SrcPort 1 + Points [5, 0] + DstBlock "Add3" + DstPort 2 + } + Line { + ZOrder 6 + SrcBlock "z\n" + SrcPort 1 + Points [21, 0] + Branch { + ZOrder 7 + Points [0, -40] + DstBlock "constK1" + DstPort 1 + } + Branch { + ZOrder 8 + Points [0, 15] + DstBlock "Product4" + DstPort 2 + } + Branch { + ZOrder 9 + DstBlock "Product4" + DstPort 1 + } + } + Line { + ZOrder 10 + SrcBlock "Add3" + SrcPort 1 + DstBlock "Add1" + DstPort 1 + } + Line { + ZOrder 11 + SrcBlock "constK" + SrcPort 1 + Points [15, 0] + DstBlock "Add1" + DstPort 2 + } + Line { + ZOrder 12 + SrcBlock "Add1" + SrcPort 1 + DstBlock "p(z)" + DstPort 1 + } + } + } + Block { + BlockType Product + Name "Product5" + SID "962" + Ports [2, 1] + Position [730, 582, 760, 613] + ZOrder 274 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "den(z)" + SID "959" + Position [775, 593, 805, 607] + ZOrder -2 + IconDisplay "Port number" + } + Line { + ZOrder 34 + SrcBlock "z\n" + SrcPort 1 + Points [5, 0] + Branch { + ZOrder 39 + DstBlock "M-" + DstPort 1 + } + Branch { + ZOrder 27 + DstBlock "M+" + DstPort 1 + } + } + Line { + ZOrder 31 + SrcBlock "M+" + SrcPort 1 + DstBlock "Product5" + DstPort 1 + } + Line { + ZOrder 40 + SrcBlock "M-" + SrcPort 1 + Points [18, 0; 0, -40] + DstBlock "Product5" + DstPort 2 + } + Line { + ZOrder 35 + SrcBlock "Product5" + SrcPort 1 + DstBlock "den(z)" + DstPort 1 + } + } + } + Block { + BlockType SubSystem + Name "h\n" + SID "1128" + Ports [1, 1] + Position [145, 76, 185, 94] + ZOrder 276 + BackgroundColor "magenta" + RequestExecContextInheritance off + System { + Name "h\n" + Location [0, 23, 1440, 896] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "586" + Block { + BlockType Inport + Name "z\n" + SID "1129" + Position [510, 223, 540, 237] + ZOrder -1 + IconDisplay "Port number" + } + Block { + BlockType Gain + Name "Gain" + SID "1130" + Position [670, 215, 700, 245] + ZOrder 277 + Gain "1/Rbob^2" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sqrt + Name "Sqrt" + SID "1131" + Position [625, 215, 655, 245] + ZOrder 246 + ShowName off + } + Block { + BlockType SubSystem + Name "denom" + SID "1132" + Ports [1, 1] + Position [555, 213, 610, 247] + ZOrder 276 + BackgroundColor "magenta" + RequestExecContextInheritance off + System { + Name "denom" + Location [0, 23, 1440, 896] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "612" + Block { + BlockType Inport + Name "z\n" + SID "1133" + Position [580, 583, 610, 597] + ZOrder -1 + IconDisplay "Port number" + } + Block { + BlockType SubSystem + Name "M+" + SID "1134" + Ports [1, 1] + Position [635, 573, 690, 607] + ZOrder 271 + BackgroundColor "magenta" + RequestExecContextInheritance off + System { + Name "M+" + Location [0, 23, 1440, 896] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "399" + Block { + BlockType Inport + Name "z\n" + SID "1135" + Position [480, 378, 510, 392] + ZOrder -1 + IconDisplay "Port number" + } + Block { + BlockType Sum + Name "Add1" + SID "1136" + Ports [2, 1] + Position [735, 347, 765, 378] + ZOrder 269 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add2" + SID "1137" + Ports [2, 1] + Position [605, 387, 635, 418] + ZOrder 264 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add3" + SID "1138" + Ports [2, 1] + Position [680, 337, 710, 368] + ZOrder 267 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Constant + Name "Constant3" + SID "1139" + Position [620, 367, 655, 383] + ZOrder 259 + ShowName off + Value "Lbob^2" + } + Block { + BlockType Constant + Name "Constant4" + SID "1140" + Position [540, 422, 575, 438] + ZOrder 260 + ShowName off + Value "Rbob^2" + } + Block { + BlockType Product + Name "Product4" + SID "1141" + Ports [2, 1] + Position [555, 377, 585, 408] + ZOrder 263 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK" + SID "1142" + Position [650, 391, 700, 419] + ZOrder 274 + ShowName off + Gain "4" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK1" + SID "1143" + Position [595, 331, 645, 359] + ZOrder 275 + ShowName off + Gain "4*Lbob" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "p(z)" + SID "1144" + Position [795, 358, 825, 372] + ZOrder -2 + IconDisplay "Port number" + } + Line { + ZOrder 1 + SrcBlock "Product4" + SrcPort 1 + DstBlock "Add2" + DstPort 1 + } + Line { + ZOrder 2 + SrcBlock "Constant4" + SrcPort 1 + Points [10, 0] + DstBlock "Add2" + DstPort 2 + } + Line { + ZOrder 3 + SrcBlock "Add2" + SrcPort 1 + DstBlock "constK" + DstPort 1 + } + Line { + ZOrder 4 + SrcBlock "constK1" + SrcPort 1 + DstBlock "Add3" + DstPort 1 + } + Line { + ZOrder 5 + SrcBlock "Constant3" + SrcPort 1 + Points [5, 0] + DstBlock "Add3" + DstPort 2 + } + Line { + ZOrder 6 + SrcBlock "z\n" + SrcPort 1 + Points [21, 0] + Branch { + ZOrder 7 + Points [0, -40] + DstBlock "constK1" + DstPort 1 + } + Branch { + ZOrder 8 + Points [0, 15] + DstBlock "Product4" + DstPort 2 + } + Branch { + ZOrder 9 + DstBlock "Product4" + DstPort 1 + } + } + Line { + ZOrder 10 + SrcBlock "Add3" + SrcPort 1 + DstBlock "Add1" + DstPort 1 + } + Line { + ZOrder 11 + SrcBlock "constK" + SrcPort 1 + Points [15, 0] + DstBlock "Add1" + DstPort 2 + } + Line { + ZOrder 12 + SrcBlock "Add1" + SrcPort 1 + DstBlock "p(z)" + DstPort 1 + } + } + } + Block { + BlockType SubSystem + Name "M-" + SID "1145" + Ports [1, 1] + Position [635, 628, 690, 662] + ZOrder 276 + BackgroundColor "magenta" + RequestExecContextInheritance off + System { + Name "M-" + Location [0, 23, 1440, 896] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "399" + Block { + BlockType Inport + Name "z\n" + SID "1146" + Position [480, 378, 510, 392] + ZOrder -1 + IconDisplay "Port number" + } + Block { + BlockType Sum + Name "Add1" + SID "1147" + Ports [2, 1] + Position [735, 347, 765, 378] + ZOrder 269 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add2" + SID "1148" + Ports [2, 1] + Position [605, 387, 635, 418] + ZOrder 264 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add3" + SID "1149" + Ports [2, 1] + Position [680, 337, 710, 368] + ZOrder 267 + ShowName off + Inputs "-+" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Constant + Name "Constant3" + SID "1150" + Position [620, 367, 655, 383] + ZOrder 259 + ShowName off + Value "Lbob^2" + } + Block { + BlockType Constant + Name "Constant4" + SID "1151" + Position [540, 422, 575, 438] + ZOrder 260 + ShowName off + Value "Rbob^2" + } + Block { + BlockType Product + Name "Product4" + SID "1152" + Ports [2, 1] + Position [555, 377, 585, 408] + ZOrder 263 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK" + SID "1153" + Position [650, 391, 700, 419] + ZOrder 274 + ShowName off + Gain "4" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK1" + SID "1154" + Position [595, 331, 645, 359] + ZOrder 275 + ShowName off + Gain "4*Lbob" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "p(z)" + SID "1155" + Position [795, 358, 825, 372] + ZOrder -2 + IconDisplay "Port number" + } + Line { + ZOrder 1 + SrcBlock "Product4" + SrcPort 1 + DstBlock "Add2" + DstPort 1 + } + Line { + ZOrder 2 + SrcBlock "Constant4" + SrcPort 1 + Points [10, 0] + DstBlock "Add2" + DstPort 2 + } + Line { + ZOrder 3 + SrcBlock "Add2" + SrcPort 1 + DstBlock "constK" + DstPort 1 + } + Line { + ZOrder 4 + SrcBlock "constK1" + SrcPort 1 + DstBlock "Add3" + DstPort 1 + } + Line { + ZOrder 5 + SrcBlock "Constant3" + SrcPort 1 + Points [5, 0] + DstBlock "Add3" + DstPort 2 + } + Line { + ZOrder 6 + SrcBlock "z\n" + SrcPort 1 + Points [21, 0] + Branch { + ZOrder 7 + Points [0, -40] + DstBlock "constK1" + DstPort 1 + } + Branch { + ZOrder 8 + Points [0, 15] + DstBlock "Product4" + DstPort 2 + } + Branch { + ZOrder 9 + DstBlock "Product4" + DstPort 1 + } + } + Line { + ZOrder 10 + SrcBlock "Add3" + SrcPort 1 + DstBlock "Add1" + DstPort 1 + } + Line { + ZOrder 11 + SrcBlock "constK" + SrcPort 1 + Points [15, 0] + DstBlock "Add1" + DstPort 2 + } + Line { + ZOrder 12 + SrcBlock "Add1" + SrcPort 1 + DstBlock "p(z)" + DstPort 1 + } + } + } + Block { + BlockType Product + Name "Product5" + SID "1156" + Ports [2, 1] + Position [730, 582, 760, 613] + ZOrder 274 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "den(z)" + SID "1157" + Position [775, 593, 805, 607] + ZOrder -2 + IconDisplay "Port number" + } + Line { + ZOrder 1 + SrcBlock "z\n" + SrcPort 1 + Points [5, 0] + Branch { + ZOrder 2 + DstBlock "M-" + DstPort 1 + } + Branch { + ZOrder 3 + DstBlock "M+" + DstPort 1 + } + } + Line { + ZOrder 4 + SrcBlock "M+" + SrcPort 1 + DstBlock "Product5" + DstPort 1 + } + Line { + ZOrder 5 + SrcBlock "M-" + SrcPort 1 + Points [18, 0; 0, -40] + DstBlock "Product5" + DstPort 2 + } + Line { + ZOrder 6 + SrcBlock "Product5" + SrcPort 1 + DstBlock "den(z)" + DstPort 1 + } + } + } + Block { + BlockType Outport + Name "h(z)" + SID "1158" + Position [715, 223, 745, 237] + ZOrder -2 + IconDisplay "Port number" + } + Line { + ZOrder 1 + SrcBlock "z\n" + SrcPort 1 + DstBlock "denom" + DstPort 1 + } + Line { + ZOrder 2 + SrcBlock "denom" + SrcPort 1 + DstBlock "Sqrt" + DstPort 1 + } + Line { + ZOrder 3 + SrcBlock "Sqrt" + SrcPort 1 + DstBlock "Gain" + DstPort 1 + } + Line { + ZOrder 4 + SrcBlock "Gain" + SrcPort 1 + DstBlock "h(z)" + DstPort 1 + } + } + } + Block { + BlockType SubSystem + Name "h1\n" + SID "864" + Ports [1, 1] + Position [145, 131, 185, 149] + ZOrder 265 + BackgroundColor "magenta" + RequestExecContextInheritance off + System { + Name "h1\n" + Location [0, 23, 1440, 896] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "467" + Block { + BlockType Inport + Name "z\n" + SID "865" + Position [495, 223, 525, 237] + ZOrder -1 + IconDisplay "Port number" + } + Block { + BlockType Gain + Name "Gain" + SID "1127" + Position [700, 215, 730, 245] + ZOrder 277 + Gain "1/Rbob^2" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sqrt + Name "Sqrt" + SID "870" + Position [640, 215, 670, 245] + ZOrder 246 + ShowName off + } + Block { + BlockType SubSystem + Name "denom" + SID "1101" + Ports [1, 1] + Position [555, 213, 610, 247] + ZOrder 276 + BackgroundColor "magenta" + RequestExecContextInheritance off + System { + Name "denom" + Location [0, 23, 1440, 896] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "612" + Block { + BlockType Inport + Name "z\n" + SID "1102" + Position [580, 583, 610, 597] + ZOrder -1 + IconDisplay "Port number" + } + Block { + BlockType SubSystem + Name "M+" + SID "1103" + Ports [1, 1] + Position [635, 573, 690, 607] + ZOrder 271 + BackgroundColor "magenta" + RequestExecContextInheritance off + System { + Name "M+" + Location [0, 23, 1440, 896] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "399" + Block { + BlockType Inport + Name "z\n" + SID "1104" + Position [480, 378, 510, 392] + ZOrder -1 + IconDisplay "Port number" + } + Block { + BlockType Sum + Name "Add1" + SID "1105" + Ports [2, 1] + Position [735, 347, 765, 378] + ZOrder 269 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add2" + SID "1106" + Ports [2, 1] + Position [605, 387, 635, 418] + ZOrder 264 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add3" + SID "1107" + Ports [2, 1] + Position [680, 337, 710, 368] + ZOrder 267 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Constant + Name "Constant3" + SID "1108" + Position [620, 367, 655, 383] + ZOrder 259 + ShowName off + Value "Lbob^2" + } + Block { + BlockType Constant + Name "Constant4" + SID "1109" + Position [540, 422, 575, 438] + ZOrder 260 + ShowName off + Value "Rbob^2" + } + Block { + BlockType Product + Name "Product4" + SID "1110" + Ports [2, 1] + Position [555, 377, 585, 408] + ZOrder 263 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK" + SID "1111" + Position [650, 391, 700, 419] + ZOrder 274 + ShowName off + Gain "4" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK1" + SID "1112" + Position [595, 331, 645, 359] + ZOrder 275 + ShowName off + Gain "4*Lbob" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "p(z)" + SID "1113" + Position [795, 358, 825, 372] + ZOrder -2 + IconDisplay "Port number" + } + Line { + ZOrder 1 + SrcBlock "Product4" + SrcPort 1 + DstBlock "Add2" + DstPort 1 + } + Line { + ZOrder 2 + SrcBlock "Constant4" + SrcPort 1 + Points [10, 0] + DstBlock "Add2" + DstPort 2 + } + Line { + ZOrder 3 + SrcBlock "Add2" + SrcPort 1 + DstBlock "constK" + DstPort 1 + } + Line { + ZOrder 4 + SrcBlock "constK1" + SrcPort 1 + DstBlock "Add3" + DstPort 1 + } + Line { + ZOrder 5 + SrcBlock "Constant3" + SrcPort 1 + Points [5, 0] + DstBlock "Add3" + DstPort 2 + } + Line { + ZOrder 6 + SrcBlock "z\n" + SrcPort 1 + Points [21, 0] + Branch { + ZOrder 7 + Points [0, -40] + DstBlock "constK1" + DstPort 1 + } + Branch { + ZOrder 8 + Points [0, 15] + DstBlock "Product4" + DstPort 2 + } + Branch { + ZOrder 9 + DstBlock "Product4" + DstPort 1 + } + } + Line { + ZOrder 10 + SrcBlock "Add3" + SrcPort 1 + DstBlock "Add1" + DstPort 1 + } + Line { + ZOrder 11 + SrcBlock "constK" + SrcPort 1 + Points [15, 0] + DstBlock "Add1" + DstPort 2 + } + Line { + ZOrder 12 + SrcBlock "Add1" + SrcPort 1 + DstBlock "p(z)" + DstPort 1 + } + } + } + Block { + BlockType SubSystem + Name "M-" + SID "1114" + Ports [1, 1] + Position [635, 628, 690, 662] + ZOrder 276 + BackgroundColor "magenta" + RequestExecContextInheritance off + System { + Name "M-" + Location [0, 23, 1440, 896] + Open off + ModelBrowserVisibility off + ModelBrowserWidth 200 + ScreenColor "white" + PaperOrientation "landscape" + PaperPositionMode "auto" + PaperType "A4" + PaperUnits "centimeters" + TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] + TiledPageScale 1 + ShowPageBoundaries off + ZoomFactor "399" + Block { + BlockType Inport + Name "z\n" + SID "1115" + Position [480, 378, 510, 392] + ZOrder -1 + IconDisplay "Port number" + } + Block { + BlockType Sum + Name "Add1" + SID "1116" + Ports [2, 1] + Position [735, 347, 765, 378] + ZOrder 269 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add2" + SID "1117" + Ports [2, 1] + Position [605, 387, 635, 418] + ZOrder 264 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Sum + Name "Add3" + SID "1118" + Ports [2, 1] + Position [680, 337, 710, 368] + ZOrder 267 + ShowName off + Inputs "-+" + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Constant + Name "Constant3" + SID "1119" + Position [620, 367, 655, 383] + ZOrder 259 + ShowName off + Value "Lbob^2" + } + Block { + BlockType Constant + Name "Constant4" + SID "1120" + Position [540, 422, 575, 438] + ZOrder 260 + ShowName off + Value "Rbob^2" + } + Block { + BlockType Product + Name "Product4" + SID "1121" + Ports [2, 1] + Position [555, 377, 585, 408] + ZOrder 263 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK" + SID "1122" + Position [650, 391, 700, 419] + ZOrder 274 + ShowName off + Gain "4" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Gain + Name "constK1" + SID "1123" + Position [595, 331, 645, 359] + ZOrder 275 + ShowName off + Gain "4*Lbob" + ParamDataTypeStr "Inherit: Inherit via internal rule" + OutDataTypeStr "Inherit: Inherit via internal rule" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "p(z)" + SID "1124" + Position [795, 358, 825, 372] + ZOrder -2 + IconDisplay "Port number" + } + Line { + ZOrder 1 + SrcBlock "Product4" + SrcPort 1 + DstBlock "Add2" + DstPort 1 + } + Line { + ZOrder 2 + SrcBlock "Constant4" + SrcPort 1 + Points [10, 0] + DstBlock "Add2" + DstPort 2 + } + Line { + ZOrder 3 + SrcBlock "Add2" + SrcPort 1 + DstBlock "constK" + DstPort 1 + } + Line { + ZOrder 4 + SrcBlock "constK1" + SrcPort 1 + DstBlock "Add3" + DstPort 1 + } + Line { + ZOrder 5 + SrcBlock "Constant3" + SrcPort 1 + Points [5, 0] + DstBlock "Add3" + DstPort 2 + } + Line { + ZOrder 6 + SrcBlock "z\n" + SrcPort 1 + Points [21, 0] + Branch { + ZOrder 7 + Points [0, -40] + DstBlock "constK1" + DstPort 1 + } + Branch { + ZOrder 8 + Points [0, 15] + DstBlock "Product4" + DstPort 2 + } + Branch { + ZOrder 9 + DstBlock "Product4" + DstPort 1 + } + } + Line { + ZOrder 10 + SrcBlock "Add3" + SrcPort 1 + DstBlock "Add1" + DstPort 1 + } + Line { + ZOrder 11 + SrcBlock "constK" + SrcPort 1 + Points [15, 0] + DstBlock "Add1" + DstPort 2 + } + Line { + ZOrder 12 + SrcBlock "Add1" + SrcPort 1 + DstBlock "p(z)" + DstPort 1 + } + } + } + Block { + BlockType Product + Name "Product5" + SID "1125" + Ports [2, 1] + Position [730, 582, 760, 613] + ZOrder 274 + ShowName off + InputSameDT off + OutDataTypeStr "Inherit: Inherit via internal rule" + RndMeth "Floor" + SaturateOnIntegerOverflow off + } + Block { + BlockType Outport + Name "den(z)" + SID "1126" + Position [775, 593, 805, 607] + ZOrder -2 + IconDisplay "Port number" + } + Line { + ZOrder 1 + SrcBlock "z\n" + SrcPort 1 + Points [5, 0] + Branch { + ZOrder 2 + DstBlock "M-" + DstPort 1 + } + Branch { + ZOrder 3 + DstBlock "M+" + DstPort 1 + } + } + Line { + ZOrder 4 + SrcBlock "M+" + SrcPort 1 + DstBlock "Product5" + DstPort 1 + } + Line { + ZOrder 5 + SrcBlock "M-" + SrcPort 1 + Points [18, 0; 0, -40] + DstBlock "Product5" + DstPort 2 + } + Line { + ZOrder 6 + SrcBlock "Product5" + SrcPort 1 + DstBlock "den(z)" + DstPort 1 + } + } + } + Block { + BlockType Outport + Name "h(z)" + SID "898" + Position [760, 223, 790, 237] + ZOrder -2 + IconDisplay "Port number" + } + Line { + ZOrder 20 + SrcBlock "z\n" + SrcPort 1 + DstBlock "denom" + DstPort 1 + } + Line { + ZOrder 21 + SrcBlock "denom" + SrcPort 1 + DstBlock "Sqrt" + DstPort 1 + } + Line { + ZOrder 23 + SrcBlock "Sqrt" + SrcPort 1 + DstBlock "Gain" + DstPort 1 + } + Line { + ZOrder 22 + SrcBlock "Gain" + SrcPort 1 + DstBlock "h(z)" + DstPort 1 + } + } + } + Block { + BlockType Outport + Name "g(z)" + SID "708" + Position [535, 58, 565, 72] + ZOrder -2 + IconDisplay "Port number" + } + Line { + ZOrder 90 + SrcBlock "Add" + SrcPort 1 + Points [5, 0] + DstBlock "Product" + DstPort 3 + } + Line { + ZOrder 117 + SrcBlock "h\n" + SrcPort 1 + DstBlock "Add" + DstPort 2 + } + Line { + ZOrder 95 + SrcBlock "Add2" + SrcPort 1 + DstBlock "Add1" + DstPort 1 + } + Line { + ZOrder 45 + SrcBlock "Divide" + SrcPort 1 + DstBlock "g(z)" + DstPort 1 + } + Line { + ZOrder 21 + SrcBlock "z\n" + SrcPort 1 + Points [13, 0] + Branch { + ZOrder 104 + DstBlock "denom" + DstPort 1 + } + Branch { + ZOrder 48 + Points [0, -70] + Branch { + ZOrder 109 + Points [0, -55] + Branch { + ZOrder 116 + DstBlock "h\n" + DstPort 1 + } + Branch { + ZOrder 89 + Points [0, -45; 121, 0] + Branch { + ZOrder 32 + Points [0, 10] + DstBlock "Product" + DstPort 2 + } + Branch { + ZOrder 31 + DstBlock "Product" + DstPort 1 + } + } + } + Branch { + ZOrder 87 + DstBlock "h1\n" + DstPort 1 + } + } + } + Line { + ZOrder 88 + SrcBlock "Constant4" + SrcPort 1 + Points [5, 0] + DstBlock "Add" + DstPort 1 + } + Line { + ZOrder 93 + SrcBlock "Product" + SrcPort 1 + DstBlock "Add2" + DstPort 2 + } + Line { + ZOrder 94 + SrcBlock "Constant1" + SrcPort 1 + Points [15, 0; 0, 15] + DstBlock "Add2" + DstPort 1 + } + Line { + ZOrder 112 + SrcBlock "constK" + SrcPort 1 + Points [25, 0; 0, -75] + DstBlock "Add1" + DstPort 2 + } + Line { + ZOrder 105 + SrcBlock "denom" + SrcPort 1 + Points [241, 0; 0, -140] + DstBlock "Divide" + DstPort 2 + } + Line { + ZOrder 110 + SrcBlock "Constant5" + SrcPort 1 + Points [5, 0] + DstBlock "Add3" + DstPort 1 + } + Line { + ZOrder 111 + SrcBlock "h1\n" + SrcPort 1 + DstBlock "Add3" + DstPort 2 + } + Line { + ZOrder 113 + SrcBlock "Add3" + SrcPort 1 + DstBlock "constK" + DstPort 1 + } + Line { + ZOrder 114 + SrcBlock "constK1" + SrcPort 1 + DstBlock "Divide" + DstPort 1 + } + Line { + ZOrder 115 + SrcBlock "Add1" + SrcPort 1 + DstBlock "constK1" + DstPort 1 + } + } + } + Block { + BlockType Scope + Name "i(t)" + SID "410" + Ports [1] + Position [465, 158, 480, 172] + ZOrder 186 + BackgroundColor "orange" + Floating off + Location [5, 226, 1212, 882] + Open on + NumInputPorts "1" + ZoomMode "xonly" + List { + ListType AxesTitles + axes1 "%" + } + List { + ListType ScopeGraphics + FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" + AxesColor "[0 0 0]" + AxesTickColor "[1 1 1]" + LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" + LineStyles "-|-|-|-|-|-" + LineWidths "[4 0.5 0.5 0.5 0.5 0.5]" + MarkerStyles "none|none|none|none|none|none" + } + ShowLegends off + TimeRange "0.005" + YMin "0" + YMax "80" + SaveName "ScopeData17" + LimitDataPoints off + } + Block { + BlockType Scope + Name "i1(t)" + SID "409" + Ports [1] + Position [465, 128, 480, 142] + ZOrder 185 + BackgroundColor "orange" + Floating off + Location [6, 72, 1372, 751] + Open off + NumInputPorts "1" + ZoomMode "yonly" + List { + ListType AxesTitles + axes1 "%" + } + List { + ListType ScopeGraphics + FigureColor "[0.5 0.5 0.5]" + AxesColor "[0 0 0]" + AxesTickColor "[1 1 1]" + LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" + LineStyles "-|-|-|-|-|-" + LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" + MarkerStyles "none|none|none|none|none|none" + } + ShowLegends off + YMin "-180" + YMax "-155" + SaveName "ScopeData16" + LimitDataPoints off + } + Block { + BlockType Scope + Name "z(t)" + SID "635" + Ports [1] + Position [205, 295, 225, 315] + ZOrder 219 + BlockRotation 270 + BackgroundColor "[0.000000, 0.819608, 0.000000]" + Floating off + Location [1, 72, 1441, 895] + Open off + NumInputPorts "1" + ZoomMode "xonly" + List { + ListType AxesTitles + axes1 "%" + } + List { + ListType ScopeGraphics + FigureColor "[0.5 0.5 0.5]" + AxesColor "[0 0 0]" + AxesTickColor "[1 1 1]" + LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" + LineStyles "-|-|-|-|-|-" + LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" + MarkerStyles "none|none|none|none|none|none" + } + ShowLegends off + TimeRange "0.003" + YMin "-0.0425" + YMax "-0.04235" + SaveName "ScopeData4" + LimitDataPoints off + } + Block { + BlockType Scope + Name "z1(t)" + SID "395" + Ports [1] + Position [266, 295, 284, 315] + ZOrder 168 + BlockRotation 270 + BackgroundColor "[0.000000, 0.819608, 0.000000]" + Floating off + Location [1, 95, 1441, 895] + Open on + NumInputPorts "1" + ZoomMode "xonly" + List { + ListType AxesTitles + axes1 "%" + } + List { + ListType ScopeGraphics + FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" + AxesColor "[0 0 0]" + AxesTickColor "[1 1 1]" + LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" + LineStyles "-|-|-|-|-|-" + LineWidths "[6 0.5 0.5 0.5 0.5 0.5]" + MarkerStyles "none|none|none|none|none|none" + } + ShowLegends off + TimeRange "0.03" + YMin "0" + YMax "30" + SaveName "ScopeData13" + LimitDataPoints off + } + Block { + BlockType Scope + Name "z2(t)" + SID "394" + Ports [1] + Position [326, 295, 344, 315] + ZOrder 167 + BlockRotation 270 + BackgroundColor "[0.000000, 0.819608, 0.000000]" + Floating off + Location [1, 72, 1441, 895] + Open off + NumInputPorts "1" + ZoomMode "xonly" + List { + ListType AxesTitles + axes1 "%" + } + List { + ListType ScopeGraphics + FigureColor "[0.5 0.5 0.5]" + AxesColor "[0 0 0]" + AxesTickColor "[1 1 1]" + LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" + LineStyles "-|-|-|-|-|-" + LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" + MarkerStyles "none|none|none|none|none|none" + } + ShowLegends off + YMin "1.03225e-09" + YMax "1.03675e-09" + SaveName "ScopeData3" + LimitDataPoints off + } + Block { + BlockType SignalViewerScope + Name "Scope1" + SID "23" + Ports [] + Position [20, 15, 60, 55] + ZOrder 21 + IOType "viewer" + Location [1, 72, 1441, 895] + Open off + NumInputPorts "1" + List { + ListType AxesTitles + axes1 "%" + } + ShowDataMarkers off + ShowLegends off + MaxDataPoints "7500" + RefreshTime 0.035000 + } + Line { + ZOrder 24 + SrcBlock "capac" + SrcPort 1 + Points [0, 0] + Branch { + ZOrder 499 + DstBlock "i(t)" + DstPort 1 + } + Branch { + ZOrder 461 + DstBlock "Multiply1" + DstPort 1 + } + } + Line { + Name "Uc''(t)" + ZOrder 25 + SrcBlock "Multiply2" + SrcPort 1 + Points [15, 0] + Branch { + ZOrder 309 + Points [0, -30] + DstBlock "capac1" + DstPort 1 + } + Branch { + ZOrder 308 + Labels [-1, 0] + DstBlock "Integ" + DstPort 1 + } + } + Line { + Name "Uc'(t)" + ZOrder 28 + Labels [1, 1] + SrcBlock "Integ" + SrcPort 1 + Points [20, 0] + Branch { + ZOrder 591 + Points [0, 45] + DstBlock "capacit1" + DstPort 1 + } + Branch { + ZOrder 26 + DstBlock "Integ1\n" + DstPort 1 + } + } + Line { + ZOrder 590 + SrcBlock "capacit1" + SrcPort 1 + Points [-70, 0; 0, -35] + DstBlock "Add" + DstPort 2 + } + Line { + ZOrder 30 + SrcBlock "Add" + SrcPort 1 + DstBlock "Multiply2" + DstPort 2 + } + Line { + ZOrder 31 + SrcBlock "capacit" + SrcPort 1 + Points [-200, 0] + DstBlock "Add" + DstPort 1 + } + Line { + ZOrder 32 + SrcBlock "Diff1" + SrcPort 1 + DstBlock "capac" + DstPort 1 + } + Line { + Name "Uc" + ZOrder 33 + Labels [-1, 1] + SrcBlock "Integ1\n" + SrcPort 1 + DstBlock "Sat" + DstPort 1 + } + Line { + FontName "Helvetica" + FontSize 9 + FontWeight "normal" + FontAngle "normal" + ZOrder 41 + SrcBlock "Sat" + SrcPort 1 + Points [0, 0] + Branch { + ZOrder 40 + Labels [0, 1] + DstBlock "Diff1" + DstPort 1 + } + Branch { + ZOrder 39 + Points [0, 65] + Branch { + ZOrder 503 + DstBlock "Uc(t)" + DstPort 1 + } + Branch { + ZOrder 502 + DstBlock "capacit" + DstPort 1 + } + } + } + Line { + ZOrder 364 + SrcBlock "Product" + SrcPort 1 + Points [-5, 0; 0, -10] + Branch { + ZOrder 483 + DstBlock "Integ2" + DstPort 1 + } + Branch { + ZOrder 132 + DstBlock "z2(t)" + DstPort 1 + } + } + Line { + ZOrder 128 + SrcBlock "Integ2" + SrcPort 1 + Points [0, 0; -5, 0] + Branch { + ZOrder 485 + DstBlock "Integ3" + DstPort 1 + } + Branch { + ZOrder 238 + DstBlock "z1(t)" + DstPort 1 + } + } + Line { + ZOrder 289 + SrcBlock "Integ3" + SrcPort 1 + Points [-5, 0] + Branch { + ZOrder 495 + Points [0, 35] + DstBlock "g" + DstPort 1 + } + Branch { + ZOrder 486 + DstBlock "L(z)" + DstPort 1 + } + Branch { + ZOrder 365 + DstBlock "z(t)" + DstPort 1 + } + } + Line { + ZOrder 311 + SrcBlock "capac1" + SrcPort 1 + Points [15, 0] + Branch { + ZOrder 498 + DstBlock "i1(t)" + DstPort 1 + } + Branch { + ZOrder 459 + DstBlock "Multiply1" + DstPort 2 + } + } + Line { + ZOrder 316 + SrcBlock "Multiply1" + SrcPort 1 + Points [0, 15] + Branch { + ZOrder 595 + Points [0, 100] + DstBlock "constK" + DstPort 1 + } + Branch { + ZOrder 359 + DstBlock "f(t)" + DstPort 1 + } + } + Line { + ZOrder 363 + SrcBlock "constK" + SrcPort 1 + DstBlock "Product" + DstPort 1 + } + Line { + ZOrder 367 + SrcBlock "g" + SrcPort 1 + Points [65, 0] + DstBlock "Product" + DstPort 2 + } + Line { + ZOrder 439 + SrcBlock "L(z)" + SrcPort 1 + Points [-45, 0] + Branch { + ZOrder 594 + Points [-69, 0; 0, -185] + DstBlock "Multiply2" + DstPort 1 + } + Branch { + ZOrder 441 + DstBlock "L(t)" + DstPort 1 + } + } + Line { + ZOrder 625 + SrcBlock "Constant" + SrcPort 1 + Points [-12, 0; 0, -8; -75, 0; 0, -22] + DstBlock "Integ2" + DstPort 2 + } + } +} diff --git a/Simulation (matlab simulink)/tipe_vars.m b/Simulation (matlab simulink)/tipe_vars.m new file mode 100755 index 0000000..89c57c6 --- /dev/null +++ b/Simulation (matlab simulink)/tipe_vars.m @@ -0,0 +1,21 @@ +R = 15 %Resistance (Ohm) +L0 = 0.0015 %initial Inductance (H) +C = 4.6e-5 %capacity (F) +U0 =800 %initial cap voltage (V) +w0=1/sqrt(L0*C) +Q=L0*w0/R + +Rbob = 0.015 %rayon bobine +Lbob = 0.06 %longueur bobine +Rproj = 0.005 %rayon projectile +Lproj = 0.025 %longueur projectile +Nspire = 500 +n = Nspire/Lbob + +gam = 10^7 +muZ = 1/(36*pi*10^9) %??? +muR= 100 +mu = muR*muZ +m = 0.02 %mass (kilogram) + +K=(pi*Rproj^4*gam*(mu*n)^2)/(8*m*Rbob^2) \ No newline at end of file diff --git a/theorie.pdf b/theorie.pdf new file mode 100644 index 0000000..e4722d6 Binary files /dev/null and b/theorie.pdf differ