Commit graph

22 commits

Author SHA1 Message Date
22f05324fa zig: 0.5.0 -> 0.5.0+e6a812c82 2020-02-02 18:24:48 +01:00
7483995316 driver: separate subtree 2020-01-11 12:43:21 +01:00
a01e9a5f2a add utilisation tracker 2020-01-01 22:59:01 +01:00
ad329b5f81 Step 11: Preemptive scheduler 2019-12-27 11:02:29 +01:00
a8c68611ce step 10: idle mode 2019-12-15 21:36:49 +01:00
e30f016977 some cleanup before the rest of the tutorial 2019-12-15 19:38:42 +01:00
9ec23055bc Step 7+8+9: usleep(), DeltaQueue 2019-12-15 19:38:37 +01:00
a527695202 Step 6: block/unblock tasks 2019-12-15 13:35:58 +01:00
f2d2ab867e Step 5: lock/unlock scheduler 2019-12-15 13:35:18 +01:00
27e6f2684b Step 3: time_used 2019-12-15 11:14:10 +01:00
ec7ee599a1 Step 2: schedule() 2019-12-15 01:13:00 +01:00
6af31b5b89 Brendan's Tutorial Step 1: done 2019-12-14 22:46:48 +01:00
8d7e7591e9 cleaned up some task details 2019-12-01 22:10:20 +01:00
5880d5296e cleaning up before kmalloc 2019-11-23 20:40:38 +01:00
902aa136c6 PIT configured, preparing for scheduling 2019-09-14 15:49:57 +02:00
bdc3b2939b compiles now, new import architecture 2019-08-22 21:59:23 +02:00
28175d9336 refactor namespacing for readability 2019-08-18 23:47:37 +02:00
d051e1b0c8 added virtio, refactoring untill compiler is fixed 2019-08-18 23:16:52 +02:00
07089c2ea1 paging done 2019-08-15 21:15:10 +02:00
e832dede16 paging almost done, endianess problem for now 2019-08-13 22:37:05 +02:00
f479edf1a3 lspci done, console ok, printf formatting ok 2019-05-12 21:12:32 +02:00
14ff4db74a first commit
boot ok
vga ok
console soon
interrupt mapping ok
isr triggers ok but doesn't iret

still lots to port from rust
2019-05-11 01:11:34 +02:00